am49pdl127ah Meet Spansion Inc., am49pdl127ah Datasheet - Page 77

• Manufacturer Part Number: am49pdl127ah
• Description: Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 16 Mbit 1m ? 16-bit Cmos Pseudo Static Ram
• Manufacturer: Meet Spansion Inc.

PSEUDO SRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled.
2. t
3. t
4. t
5. A write occurs during the overlap (t
December 18, 2003
when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
write to the end of write.
CW
WR
AS
Parameter
Symbol
is measured from the address valid to the beginning of write.
t
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
t
t
t
t
t
WHZ
t
t
t
t
t
WC
AW
BW
WP
WR
DW
OW
Cw
DH
AS
Address
CE1#s
CE2s
WE#
Data In
Data Out
Description
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Figure 28. Pseudo SRAM Write Cycle—WE# Control
A D V A N C E
WP
) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low
Data Undefined
High-Z
Am49PDL127AH/Am49PDL129AH
(See Note 3)
t
AS
I N F O R M A T I O N
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
t
WR
WHZ
(See Note 1)
(See Note 1)
t
applied in case a write ends as CE1#s or WE# going high.
AW
t
(See Note 4)
WC
t
t
CW
CW
t
WP
t
61
55
50
50
50
50
DW
Data Valid
WP
Speed
is measured from the beginning of
25
25
0
0
0
5
t
DH
t
t
WR
OW
70
70
55
55
55
55
High-Z
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
75