am49pdl127ah Meet Spansion Inc., am49pdl127ah Datasheet - Page 53

am49pdl127ah

Manufacturer Part Number

am49pdl127ah

Description

Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 16 Mbit 1m ? 16-bit Cmos Pseudo Static Ram

Manufacturer

Meet Spansion Inc.

Datasheet

1.AM49PDL127AH.pdf (82 pages)

Current page: 53 of 82
Download datasheet (2Mb)

Legend:

DYB = Dynamic Protection Bit

OW = Address (A7:A0) is (00011010)

PD[3:0] = Password Data (1 of 4 portions)

PPB = Persistent Protection Bit

PWA = Password Address. A1:A0 selects portion of password.

PWD = Password Data being verified.

PL = Password Protection Mode Lock Address (A7:A0) is (00001010)

RD(0) = Read Data DQ0 for protection indicator bit.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are

4. During unlock and command cycles, when lower address bits are

5. The reset command returns device to reading array.

6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6

7. Data is latched on the rising edge of WE#.

8. Entire command sequence must be entered for each portion of

9. Command sequence returns FFh if PPMLB is set.

December 18, 2003

Command

(Notes)

Reset

SecSi Sector Entry 3

SecSi Sector Exit

SecSi Protection

Bit Program (5, 6)

SecSi Protection

Bit Status

Password Program

(5, 7, 8)

Password Verify (6,

8, 9)

Password Unlock

(7, 10, 11)

PPB Program (5, 6,

12, 17)

PPB Status

All PPB Erase (5,

6, 13, 14)

PPB Lock Bit Set

(17)

PPB Lock Bit

Status (15)

DYB Write (7)

DYB Erase (7)

DYB Status (6, 18) 4

PPMLB Program

(5, 6, 12)

PPMLB Status (5)

SPMLB Program

(5, 6, 12)

SPMLB Status (5)

See Table 1 for description of bus operations.

write operations.

555 or 2AAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares.

validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0

in cycle 6, program command must be issued and verified again.

password.

1 XXX

Addr Data Addr Data Addr Data

555

2AA

Table 17. Sector Protection Command Definitions

A D V A N C E

555

Am49PDL127AH/Am49PDL129AH

PWA[0-3]

(SA)WP

XX[0-3]

PWA[0]

Addr

I N F O R M A T I O N

PWD[0-3]

Bus Cycles (Notes 1-4)

PWD[0]

PD[0-3]

RD(1)

RD(0)

Data

RD(1) = Read Data DQ1 for PPB Lock status.

SA = Sector Address where security command applies. Address bits

A21:A12 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)

WP = PPB Address (A7:A0) is (00000010) (NoteTable.16

30535a1.fm)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

10. The password is written over four consecutive cycles, at

11. A 2 µs timeout is required between any two portions of password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been

15. DQ1 = 1 if PPB locked, 0 if unlocked.

16. For PDL128G and PDL640G, the WP address is 0111010. The

17. Following the final cycle of the command sequence, the user must

18. If checking the DYB status of sectors in multiple banks, the user

addresses 0-3.

fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command

must be issued and verified again. Before issuing erase

command, all PPBs should be programmed to prevent PPB

overerasure.

EP address (PPB Erase Address) is 1111010.

write the first three cycles of the Autoselect command and then

write a Reset command.

must follow Note 17 before crossing a bank boundary.

(SA)WP

PWA[1]

Addr

(SA)

PWD[1]

RD (0)

RD(0)

Data

(SA)WP

PWA[2]

Addr

PWD[2]

RD(0)

Data

PWA[3]

Addr

PWD[3]

Data

am49pdl127ah Meet Spansion Inc., am49pdl127ah Datasheet - Page 53

am49pdl127ah

Related parts for am49pdl127ah