th50vsf2580 TOSHIBA Semiconductor CORPORATION, th50vsf2580 Datasheet - Page 44

• Manufacturer Part Number: th50vsf2580
• Description: Sram And Flash Memory Mixed Multi-chip Package
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SRAM DATA RETENTION CHARACTERISTICS
Notes:
V
I
t
t
(1) Read cycle time
CE2S-CONTROLLED DATA RETENTION MODE (see Note 3)
CE
CCS4
CDR
r
(1)
(2)
(3)
DH
SYMBOL
1
S
-CONTROLLED DATA RETENTION MODE (see Note 1)
In
CE2S ≤ 0.2 V or CE2S ≥ V
When
V
In CE2S-Controlled Data Retention Mode the device enters Minimum Standby Current Mode when
CE2S ≤ 0.2 V.
CCs
V
2.7 V
V
2.7 V
GND
GND
CE
CCs
CCs
V
V
V
IH
IH
IL
from 3.6 V to 2.4 V.
1
Data Retention Supply Voltage for SRAM
SRAM Standby Current
Chip-Deselect-to-Data-Retention-Mode Time
Recovery Time
CE
S
CE
V
V
CE2S
-Controlled Data Retention Mode the device enters Minimum Standby Current Mode when
1
CCs
CCs
S
1
S
is at V
IH
(2.2 V), the SRAM standby current is the same as I
PARAMETER
CCs
(See Note 2)
t
CDR
t
− 0.2 V.
CDR
V
V
DH
DH
= 3.0 V
= 3.6 V
Data Retention Mode
Data Retention Mode
V
CCs
(Ta = = = = -40°~85°C)
0.2 V
− 0.2 V
t
RC
MIN
1.5


0
(1)
TH50VSF2580/2581AASB
TYP.





(See Note 2)
CCS3
t
r
t
2001-10-26 44/50
r
during the transition of
MAX
3.6


5
7
UNIT
µA
ns
ns
V