am41dl6408h Meet Spansion Inc., am41dl6408h Datasheet - Page 5

• Manufacturer Part Number: am41dl6408h
• Description: Stacked Multi-chip Package Mcp Flash Memory And Sram 64 Megabit 8 M X 8-bit/4 M X 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 8 Mbit 1 M X 8-bit/512 K X 16-bit Static Ram
• Manufacturer: Meet Spansion Inc.

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Common Flash Memory Interface (CFI) . . . . . . . 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 27
November 24, 2003
Word/Byte Configuration ........................................................ 13
Requirements for Reading Array Data ................................... 13
Writing Commands/Command Sequences ............................ 14
Simultaneous Read/Write Operations with Zero Latency ....... 14
Standby Mode ........................................................................ 14
Automatic Sleep Mode ........................................................... 15
RESET#: Hardware Reset Pin ............................................... 15
Output Disable Mode .............................................................. 15
Sector/Sector Block Protection and Unprotection .................. 19
Write Protect (WP#) ................................................................ 19
Temporary Sector Unprotect .................................................. 20
SecSi™ (Secured Silicon) Sector Flash Memory Region ...... 22
Hardware Data Protection ...................................................... 23
Reading Array Data ................................................................ 27
Reset Command ..................................................................... 27
Autoselect Command Sequence ............................................ 27
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 27
Byte/Word Program Command Sequence ............................. 28
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
SRAM Word Mode, CIOs = V
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
SRAM Byte Mode, CIOs = V
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SRAM Word Mode, CIOs = V
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
Byte Mode, CIOs = V
Accelerated Program Operation .......................................... 14
Autoselect Functions ........................................................... 14
Table 5. Am29DL640H Sector Architecture ....................................15
Table 6. Bank Address ....................................................................18
Table 7. SecSi™ Sector Addresses ...............................................18
Table 8. Am29DL640H Boot Sector/Sector Block Addresses for
Protection/Unprotection ...................................................................19
Table 9. WP#/ACC Modes ..............................................................20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21
Figure 3. SecSi Sector Protect Verify.............................................. 23
Low V
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Table 10. CFI Query Identification String ........................................ 24
System Interface String................................................................... 24
Table 12. Device Geometry Definition ............................................ 24
Table 13. Primary Vendor-Specific Extended Query ...................... 26
Unlock Bypass Command Sequence .................................. 28
Figure 4. Program Operation .......................................................... 29
CC
Write Inhibit ........................................................... 23
SS
..................................................................13
SS
CC
CC
..................................................... 10
......................................................11
.....................................................12
A D V A N C E
IL
SS
; SRAM
IH
IH
Am41DL6408H
;
;
;
I N F O R M A T I O N
Write Operation Status . . . . . . . . . . . . . . . . . . . . 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
SRAM DC and Operating Characteristics . . . . . 38
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Chip Erase Command Sequence ........................................... 29
Sector Erase Command Sequence ........................................ 29
Erase Suspend/Erase Resume Commands ........................... 30
DQ7: Data# Polling ................................................................. 32
RY/BY#: Ready/Busy# ............................................................ 33
DQ6: Toggle Bit I .................................................................... 33
DQ2: Toggle Bit II ................................................................... 34
Reading Toggle Bits DQ6/DQ2 ............................................... 34
DQ5: Exceeded Timing Limits ................................................ 34
DQ3: Sector Erase Timer ....................................................... 34
SRAM CE#s Timing ................................................................ 41
Flash Read-Only Operations ................................................. 42
Hardware Reset (RESET#) .................................................... 43
Word/Byte Configuration (CIOf) .............................................. 44
Erase and Program Operations .............................................. 45
Temporary Sector Unprotect .................................................. 50
Alternate CE#f Controlled Erase and Program Operations .... 52
SRAM Read Cycle .................................................................. 54
SRAM Write Cycle .................................................................. 56
Figure 5. Erase Operation.............................................................. 30
Table 14. Am29DL640H Command Definitions .............................. 31
Figure 6. Data# Polling Algorithm .................................................. 32
Figure 7. Toggle Bit Algorithm........................................................ 33
Table 15. Write Operation Status ................................................... 35
Figure 8. Maximum Negative Overshoot Waveform ...................... 36
Figure 9. Maximum Positive Overshoot Waveform........................ 36
Figure 10. I
Automatic Sleep Currents) ............................................................. 39
Figure 11. Typical I
Figure 12. Test Setup.................................................................... 40
Figure 13. Input Waveforms and Measurement Levels ................. 40
Figure 14. Timing Diagram for Alternating Between
SRAM to Flash ............................................................................... 41
Figure 15. Read Operation Timings ............................................... 42
Figure 16. Reset Timings ............................................................... 43
Figure 17. CIOf Timings for Read Operations................................ 44
Figure 18. CIOf Timings for Write Operations................................ 44
Figure 19. Program Operation Timings.......................................... 46
Figure 20. Accelerated Program Timing Diagram.......................... 46
Figure 21. Chip/Sector Erase Operation Timings .......................... 47
Figure 22. Back-to-back Read/Write Cycle Timings ...................... 48
Figure 23. Data# Polling Timings (During Embedded Algorithms). 48
Figure 24. Toggle Bit Timings (During Embedded Algorithms)...... 49
Figure 25. DQ2 vs. DQ6................................................................. 49
Figure 26. Temporary Sector Unprotect Timing Diagram .............. 50
Figure 27. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 51
Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 53
Figure 29. SRAM Read Cycle—Address Controlled...................... 54
Figure 30. SRAM Read Cycle ........................................................ 55
Figure 31. SRAM Write Cycle—WE# Control ................................ 56
CC1
Current vs. Time (Showing Active and
CC1
vs. Frequency ............................................ 39
3