hi-3717 QuickLogic Corp, hi-3717 Datasheet - Page 6

• Manufacturer Part Number: hi-3717
• Description: Single-rail Arinc 717 Protocol Ic With Spi Interface
• Manufacturer: QuickLogic Corp

REGISTER DESCRIPTIONS
OP Code R/W
6 - 4
2-1
Bit
7
3
0
0xEA
0xFE
CONTROL REGISTER 0: CTRL0
0x6A
0xE4
0xE2
0xE6
0xE8
0xF2
0xF6
0x64
0x62
0x72
0x74
0xC*
0x2*
Read: SPI Op-code 0xE4
Write: SPI Op-code 0x64
* In the case of FAST instructions, the last four bits of the instruction byte are data
SLEW1:0
32WPS
RXSEL
BR2:0
Name
-
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R/W Default Description
R/W
R/W
R/W
R/W
R/W
# Data
bytes
1
1
1
2
2
1
1
1
1
1
1
2
2
4
1
0
0
0
0
0
Write Control Register 0
Write Control Register 1
Write Receiver FIFO Status Pin Assignment Register
Write Word Count Utility Register
Write Transmit FIFO word
Fast Write Transmit FIFO Word
Read Control Register 0
Read Control Register 1
Read Receive FIFO Status Register
Read Transmit FIFO Status Register
Read Receive FIFO Status Pin Assignment Register
Read Word Count Utility Register
Read Receive FIFO Word
Read Receive FIFO Word and Word Count
Fast Read Receive FIFO
pin.
Not Used. Always reads a “0”
Setting these bits sets the ARINC 717 data rate for both the receive and transmit data.
Setting this bit overrides the state of BR2:0 and sets the data rate at 384 Bits/sec. (32 words/sec.)
Setting these bits controls the nominal slew rate on both the HBP & BPRZ transmit channel outputs.
Selects either the HBP (”0”) or BPRZ (”1”) Receiver. This bit is logically OR’d with the RSEL input
000
001
010
011
100
101
110
111
00
01
10
11
768 Bits/sec. ( 64 words/sec.)
1536 Bits/sec. (128 words/sec.)
3072 Bits/sec. (256 words/sec.)
6144 Bits/sec. (512 words /sec.)
12288 Bits/sec. (1024 words/sec.)
24576 Bits/sec. (2048 words/sec.)
49152 Bits/sec. (4096 words/sec.)
98304 Bits/sec. (8192 words/sec.)
7.5
10.0
10.0
1.5
HOLT INTEGRATED CIRCUITS
m
m
TABLE 2. SPI Instruction Set
m
m
s
s ( Same as ARINC 429 High Speed)
s ( Same as ARINC 429 Low Speed)
s ( Same as ARINC 429 Low Speed)
HI-3717
TABLE 3.
MSB
X
7
6
6
5
4
DESCRIPTION
3
2
1
LSB
0