hi-3717 QuickLogic Corp, hi-3717 Datasheet - Page 5

• Manufacturer Part Number: hi-3717
• Description: Single-rail Arinc 717 Protocol Ic With Spi Interface
• Manufacturer: QuickLogic Corp

Figure 3 and Figure 4 show read and write timing as it appears
for a single-byte and dual-byte register operation. The
instruction op code is immediately followed by a data byte
comprising the 8-bit data word read or written. For a register
read or write,
Table 2 summarizes the HI-3717 SPI instruction set.
SCK
SPI Mode 0
SI
SO
CS
High Z
CS
MSB
is negated after the data byte is transferred.
SCK
SI
SO
CS
0
1
High Z
Op-Code Byte
2
3
MSB
0
4
1
5
FIGURE 3. Single-Byte Read From a Register
Op-Code Byte
2
6
FIGURE 4. 2-Byte SPI Write Example
LSB
3
7
HOLT INTEGRATED CIRCUITS
MSB
4
0
5
1
6
2
Data Byte 0
HI-3717
LSB
7
3
5
MSB
0
4
Note: SPI Instruction op-codes not shown in Table 2 are
“reserved” and must not be used. Further, these op-codes will
not provide meaningful data in response to a read instruction.
Two instruction bytes cannot be “chained”;
after each instruction, and then reasserted for the following
Read or Write instruction.
1
5
2
6
Data Byte
LSB MSB
3
7
4
0
5
1
6
2
Data Byte 1
LSB
LSB MSB
7
3
Host may continue to assert
here to write sequential byte(s)
when allowed by the SPI instruction.
Each byte needs 8 SCK clocks.
4
Host may continue to assert
here to read sequential byte(s)
when allowed by the instruction.
Each byte needs 8 SCK clocks.
High Z
5
6
LSB
CS
7
must be negated
CS
CS