hi-3111pstf Holt Integrated Circuits, Inc., hi-3111pstf Datasheet - Page 31

• Manufacturer Part Number: hi-3111pstf
• Description: Avionics Can Controller With Integrated Transceiver
• Manufacturer: Holt Integrated Circuits, Inc.

HI-3110 SPI COMMANDS
For the HI-3110, each SPI read or write operation begins
with an 8-bit command byte transferred from the host to the
device after assertion of
reception is half-duplex, the host discards the dummy byte
it receives while serially transmitting the command byte.
Figures 10 and 11 show read and write timing as it appears
for a single-byte and dual-byte register operation. The
command byte is immediately followed by a data byte
comprising the 8-bit data word read or written. For a single
register read or write,
transferred.
HOST SERIAL PERIPHERAL INTERFACE, cont.
SCK
SPI Mode 0
SI
SO
CS
High Z
MSB
SCK
SI
SO
CS
0
1
High Z
CS
Op-Code Byte
2
CS
is negated after the data byte is
3
. Since HI-3110 command byte
MSB
0
4
1
5
Op-Code Byte
Figure 10. Single-Byte Read From a Register
2
6
LSB
3
7
HOLT INTEGRATED CIRCUITS
Figure 11. 2-Byte Write example
MSB
4
0
5
1
6
2
Data Byte 0
HI-3110
LSB
7
3
31
MSB
0
4
Multiple byte read or write cycles may be performed by
transferring more than one byte before
Tables 2 - 5 define the required number of bytes for each
instruction.
Note: SPI Instruction op-codes not shown in Tables 2 - 5
are “reserved” and must not be used. Further, these op-
codes will not provide meaningful data in response to read
commands.
Two instruction bytes cannot be “chained”;
be negated after the command, then reasserted for the
following Read or Write command.
1
5
2
6
Data Byte
LSB MSB
3
7
4
0
5
1
6
2
Data Byte 1
LSB
LSB MSB
7
3
Host may continue to assert
here to write sequential byte(s)
when allowed by the SPI instruction.
Each byte needs 8 SCK clocks.
4
Host may continue to assert
here to read sequential word(s)
when allowed by the instruction.
Each word needs 8 SCK clocks.
High Z
5
6
LSB
7
CS
is negated.
CS
CS
must
CS