hi-3593 Holt Integrated Circuits, Inc., hi-3593 Datasheet - Page 14

• Manufacturer Part Number: hi-3593
• Description: 3.3v Arinc 429 Dual Receiver, Single Transmitter With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

SERIAL PERIPHERAL INTERFACE
SERIAL PERIPHERAL INTERFACE (SPI) BASICS
The HI-3593 uses an SPI synchronous serial interface for
host access to internal registers and data FIFOs. Host
serial communication is enabled through the Chip Select
(
consisting of Serial Data Input (SI) from the host, Serial
Data Output (SO) to the host and Serial Clock (SCK). All
read / write cycles are completely self-timed.
The SPI (Serial Peripheral Interface) protocol specifies
master and slave operation; the HI-3593 operates as an
SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible
CPHA
Without describing details of the SPI modes, the HI-3593
operates in mode 0 where input data for each device (
master and slave) is clocked on the rising edge of SCK,
and output data for each device changes on the falling
edge (CPHA = 0, CPOL = 0). Be sure to set the host SPI
logic for mode 0.
As seen in Figure 5, SPI Mode 0 holds SCK in the low state
when idle.
CS
SCK (SPI Mode 0)
SO
CS
SI
) pin, and is accessed via a three-wire interface
combinations define four possible "SPI Modes".
High Z
FIGURE 5. Generalized Single-Byte Transfer Using SPI Protocol Modes 0
MSB
MSB
0
1
HOLT INTEGRATED CIRCUITS
CPOL-
2
HI-3593
14
3
The SPI protocol transfers serial data as 8-bit bytes. Once
CS
latch input data into the master and slave devices, starting
with each byte’s most-significant bit. The HI-3593 SPI can
be clocked at 10 MHz.
Multiple bytes may be transferred when the host holds
low after the first byte transferred, and continues to clock
SCK in multiples of 8 clocks.
select terminates the serial transfer and reinitializes the
HI-3593 SPI for the next transfer. If
full byte is clocked by SCK, the incomplete byte clocked
into the device SI pin is discarded.
In the general case, both master and slave simultaneously
send and receive serial data (full duplex), per Figure 5
below. However the HI-3593 operates half duplex,
maintaining high impedance on the SO output, except
when actually transmitting serial data. When the HI-3593
is sending data on SO during read operations, activity on
its SI input is ignored. Figures 6 and 7 show actual
behavior for the HI-3593 SO output.
chip select is asserted, the next 8 rising edges on SCK
4
5
6
A rising edge on
LSB
LSB
CS
7
goes high before a
High Z
CS
chip
CS