hi-3587 Holt Integrated Circuits, Inc., hi-3587 Datasheet - Page 6

• Manufacturer Part Number: hi-3587
• Description: Transmitter With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
TIMING DIAGRAMS
The word counter detects when all loaded positions have been
transmitted and sets the Status Register transmitter ready flag,
SR3, high.
TRANSMITTER PARITY
The parity generator counts the Ones in the 31-bit word. If control
register bit CR9 is set to a “0”, the 32nd bit transmitted will make
parity odd. If the control bit is a “1”, the parity is even. Setting CR3
to “0” bypasses the parity generator, and allows 32 bits of data to be
transmitted.
LINE DRIVER OPERATION
The line driver in the HI-3587 directly drives the ARINC 429 bus.
The two ARINC outputs (AOUT37 and BOUT37) provide a
differential voltage to produce a +10V One, a -10V Zero, and a 0
Volt Null. Control Register bit CR10 controls both the transmitter
data rate and the slope of the differential output signal.
additional hardware is required to control the slope.
Transmit timing is derived from a 1MHz reference clock. Control
register bit CR1 determines the reference clock source. If CR1
equals ”0,” a 50% duty cycle 1MHz clock should be applied to the
ACLK input pin. If CR1 equals ”1,” the SPI clock SCK is used as
the reference. SPI op code 07 hex is used to provide the HI-3587
with the correct division ratio to generate a 1 MHz reference from
SCK.
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
SCK
SCK
CS
CS
SO
SI
t
CHH
Hi Impedance
t
SCKH
HIGH SPEED
t
DS
10 Clocks
40 Clocks
5 Clocks
5 Clocks
t
SCKL
t
MSB
DV
MSB
LOW SPEED
t
CES
HOLT INTEGRATED CIRCUITS
320 Clocks
80 Clocks
40 Clocks
40 Clocks
SERIAL INPUT TIMING DIAGRAM
SERIAL OUTPUT TIMING DIAGRAM
t
t
CYC
CYC
t
DH
HI-3587
No
6
Loading Control Register bit CR10 to “0” causes a 100 Kbit/s data
rate and a slope of 1.5 µs on the ARINC outputs. Loading CR10 to
“1” causes a 12.5 Kbit/s data rate and a slope of 10 µs. Timing is
set by an on-chip resistor and capacitor and tested to be within
ARINC 429 requirements.
LINE DRIVER OUTPUT PINS
The HI-3587 AOUT37 and BOUT37 pins have 37.5 Ohms in
series with each line driver output, and may be directly connected
to an ARINC 429 bus. The alternate AOUT27 and BOUT27 pins
have 27 ohms of internal series resistance and require external 10
ohm resistors at each pin. AOUT27 and BOUT27 are for
applications where external series resistance is applied, usually
for lightning protection.
POWER SUPPLY SEQUENCING
Power supply sequencing should be controlled to prevent large
currents during supply turn-on and turn-off. The recommended
sequence is V+ followed by V
most positive supply. The V- supply is not critical and can be
applied at any time.
MASTER RESET (MR)
Application of a Master Reset causes immediate termination of
data transmission. The transmit FIFO is cleared. Status Register
FIFO flags and FIFO status output signal TFLAG is also cleared.
The Control Register is not affected by a Master Reset.
t
SCKR
t
SCKF
DD
LSB
, always ensuring that V+ is the
t
t
CEH
CHZ
LSB
t
t
CPH
CPH
Hi Impedance