hi-3587 Holt Integrated Circuits, Inc., hi-3587 Datasheet - Page 5

• Manufacturer Part Number: hi-3587
• Description: Transmitter With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
ARINC 429 DATA FORMAT
Control Register bit CR11 controls how individual bits in the
transmitted ARINC word are mapped to the HI-3587 SPI data word
bits during data read or write operations.
describes this mapping:
TRANSMITTER
FIFO OPERATION
The Transmit FIFO is loaded with ARINC 429 words awaiting
transmission. SPI op code 0E hex writes up to 32 ARINC words
into the FIFO, starting at the next available FIFO location. If Status
Register bit SR3 equals “1” (FIFO empty), then up to 32 words (32
bits each) may be loaded.
then only the available positions may be loaded. If all 32 positions
are full, Status Register bit SR5 is asserted. Further attempts to
load the Transmit FIFO are ignored until at least one ARINC word is
transmitted.
ARINC bit 8
ARINC bit 1
CR11=0
CR11=1
SPI
bit
SCK
SO
CS
SI
1
2
7
2
LOAD SHIFT REGISTER
32 BIT PARALLEL
3
6
3
Table 2. SPI / ARINC bit-mapping
32 x 32 FIFO
SPI INTERFACE
4
5
4
5
4
5
6
3
6
If Status Register bit SR3 equals “0”
7
2
7
SPI COMMANDS
SPI COMMANDS
8
1
8
9
9
9
FIGURE 1.
10
10
10
The following table
ADDRESS
LOAD
HOLT INTEGRATED CIRCUITS
BIT CLOCK
WORD CLOCK
11 - 31
11 - 31
11 - 31
Data
Data
TRANSMITTER BLOCK DIAGRAM
GENERATOR
HI-3587
CR3, CR9
PARITY
32
32
32
CR10, CR1
5
The Transmit FIFO half-full flag (Status Register bit SR4) equals “0”
when the Transmit FIFO contains less than 16 words. When SR4
equals “0”, the system microprocessor can safely initiate a 16-word
ARINC block-write sequence.
In normal operation (Control Register bit CR3 = ”1”), the 32nd bit
transmitted is a word parity bit. Odd or even parity is selected by
programming Control Register bit CR9 to a “0” or “1” respectively. If
Control Register bit CR3 equals “0”, all 32 bits loaded into the
Transmit FIFO are treated as data and are transmitted.
SPI op code 11 hex asynchronously clears all data in the Transmit
FIFO.
DATA TRANSMISSION
If Control Register bit CR13 equals “1”, ARINC 429 data is
transmitted immediately following the
instruction that loaded data into the Transmit FIFO. Loading
Control Register bit CR13 to “0” allows the software to control
transmission timing; each time a 12 hex SPI op code is executed,
all loaded Transmit FIFO words are transmitted. If new words are
loaded into the Transmit FIFO before transmission stops, the new
words will also be output. Once the Transmit FIFO is empty and
transmission of the last word is complete, the FIFO can be loaded
with new data which is held until the next SPI 12 hex instruction is
executed. Once transmission is enabled, the FIFO positions are
incremented with the top register loading into the data transmission
shift register. Within 2.5 data clocks the first data bit appears at
AOUT and BOUT. The 31 or 32 bits in the data transmission shift
register are presented sequentially to the outputs in the ARINC 429
format with the following timing:
CLOCK
DATA
SEQUENCER
NULL TIMER
DATA AND
WORD COUNTER
FIFO CONTROL
DATA CLOCK
SEQUENCER
WORD GAP
COUNTER
LOADING
DIVIDER
AND
AND
FIFO
BIT
SEQUENCE
WORD COUNT
INCREMENT
START
LINE DRIVER
CS
AOUT
BOUT
rising edge of the SPI
CR12
ACLK
SR3
SR4
SR5