hi-3585 Holt Integrated Circuits, Inc., hi-3585 Datasheet - Page 6

• Manufacturer Part Number: hi-3585
• Description: Terminal Ic With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the
parity bit. If the result is odd, a "0" appears in the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending on the state of Control
Register bits CR2, CR6, CR7 and CR8, the received 32-bit ARINC
word is then checked for correct decoding and label match before
it is loaded into the 32 x 32 Receive FIFO. ARINC words that do
not match required 9th and 10th ARINC bit and do not have a label
match are ignored and are not loaded into the Receive FIFO. The
adjacent table describes this operation.
CONTROL BITS
CR2, CR6-8
RFLAG
ZEROS
ONES
NULL
CONTROL
LOAD
FIFO
EOS
LOOK-UP
256-BIT
LABEL
TABLE
SCK
CS
SO
SI
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
/
COMPARE
DECODE
LABEL /
FIGURE 2.
32 BIT SHIFT REGISTER
SPI INTERFACE
HOLT INTEGRATED CIRCUITS
32 X 32
FIFO
RECEIVER BLOCK DIAGRAM
HI-3585
WORD GAP
6
BIT CLOCK
CR2
DATA
START
0
1
1
0
0
1
1
1
1
CONTROLBITS
CR0, CR1
PARITY
CHECK
ARINC word
WORD GAP
SEQUENCE
DETECTION
matches
Enabled
CONTROL
TABLE 3. FIFO LOADING CONTROL
ERROR
TIMER
label
Yes
Yes
Yes
No
No
No
X
X
X
32ND
BIT
END
ERROR
CLOCK
CR6
SEQUENCE
BIT CLOCK
COUNTER
END OF
0
0
0
1
1
1
1
1
1
OPTION
CLOCK
AND
BIT
ARINC word
bits 10, 9
CR7, 8
match
Yes
Yes
Yes
No
No
No
X
X
X
CLOCK
Ignore data
Ignore data
Ignore data
Ignore data
Ignore data
Load FIFO
Load FIFO
Load FIFO
Load FIFO
ACLK
FIFO