hi-3588pqt Holt Integrated Circuits, Inc., hi-3588pqt Datasheet - Page 7

• Manufacturer Part Number: hi-3588pqt
• Description: Receiver With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
TIMING DIAGRAMS
MASTER RESET (MR)
Assertion of Master Reset causes immediate termination of data
reception. The receive FIFO, Status Register FIFO flags and the
FIFO status RFLAG pin is also cleared. The Control Register is
not affected by Master Reset.
ARINC DATA
TXAOUT
TXBOUT
RFLAG
SCK
SCK
CS
CS
SO
SI
SO
CS
SI
t
CHH
BIT 31
DATA
Hi Impedance
ARINC BIT
BIT 30
t
SCKH
t
DS
BIT 32
NULL
t
RFLG
t
SCKL
SPI INSTRUCTION 08h, (or 09h)
DATA
t
MSB
t
DV
RXR
MSB
BIT 31
t
CES
HOLT INTEGRATED CIRCUITS
DATA RATE - EXAMPLE PATTERN
NULL
SERIAL INPUT TIMING DIAGRAM
SERIAL OUTPUT TIMING DIAGRAM
t
t
CYC
CYC
t
t
SPIF
DH
WORD 1
RECEIVER OPERATION
ARINC
DATA
HI-3588
BIT 32
7
WORD 2)
(ARINC
NULL
t
SCKR
WORD 3)
(ARINC
t
SCKF
WORD GAP
LSB
t
t
CEH
CHZ
LSB
NEXT WORD
BIT 1
t
t
CPH
CPH
Hi Impedance