hi-3588pqt Holt Integrated Circuits, Inc., hi-3588pqt Datasheet - Page 5

• Manufacturer Part Number: hi-3588pqt
• Description: Receiver With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
ARINC 429 RECEIVER
ARINC BUS INTERFACE
Figure 1 shows the input circuit for the ARINC 429 line receiver. The
ARINC 429 specification requires the following detection levels:
The HI-3588 guarantees recognition of these levels with a common
mode voltage with respect to GND less than ±30V for the worst case
condition (3.15V supply and 13V signal level). Design tolerances
guarantee detection of the above levels, so the actual acceptance
ranges are slightly larger. If the ARINC signal (including nulls) is
outside the differential voltage ranges, the HI-3588 receiver rejects
the data.
RECEIVER LOGIC OPERATION
Figure 2 is a block diagram showing receiver logic.
BIT TIMING
The ARINC 429 specification defines the following timing toler-
ances for received data:
The HI-3588 accepts signals within these tolerances and rejects
signals outside these tolerances. Receiver logic achieves this as
described below:
RINA-40
RINB-40
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
RINA
RINB
1. An accurate 1MHz clock source is required to validate the
receive signal timing. Less than 0.1% error is recommended.
2. The receiver uses three separate 10-bit sampling shift reg-
isters for Ones detection, Zeros detection and Null detection.
When the input signal is within the differential voltage range
for any shift register’s state (One Zero or Null) sampling
clocks a high bit into that register. When the receive signal is
outside the differential voltage range defined for any shift reg-
STATE
ZERO
NULL
ONE
FIGURE 1. ARINC RECEIVER INPUT
GND
GND
VDD
VDD
100K BPS ± 1%
DIFFERENTIAL VOLTAGE
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
HIGH SPEED
5 µsec ± 5%
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
DIFFERENTIAL
AMPLIFIERS
34.5 to 41.7 µsec
12K -14.5K BPS
LOW SPEED
10 ± 5 µsec
10 ± 5 µsec
HOLT INTEGRATED CIRCUITS
COMPARATORS
ONE
NULL
ZERO
HI-3588
5
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the parity
bit. If the result is odd, a "0" appears in the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS).
Register bits CR2, and CR6 through CR8, the received 32-bit
ARINC word is then checked for correct decoding and label match
before it is loaded into the 32 x 32 Receive FIFO. ARINC words that
do not match required 9th and 10th ARINC bit and do not have a
label match are ignored and are not loaded into the Receive FIFO.
The table below describes this operation.
CR2
0
1
1
0
0
1
1
1
1
ister, a low bit is clocked. Only one shift register can clock a
high bit for any given sample. All three registers clock low
bits if the differential input voltage is between defined state
voltage bands.
Valid data bits require at least three consecutive One or Zero
samples (three high bits) in the upper half of the Ones or Ze-
ros sampling shift register, and at least three consecutive Null
samples (three high bits) in the lower half of the Null sampling
shift register within the data bit interval.
A word gap Null requires at least three consecutive Null sam-
ples (three high bits) in the upper half of the Null sampling
shift register and at least three consecutive Null samples
(three high bits) in the lower half of the Null sampling shift reg-
ister. This guarantees the minimum pulse width.
3. To validate the receive data bit rate, each bit must follow
its preceding bit by not less than 8 samples and not more
than 12 samples. With exactly 1MHz input clock frequency,
the acceptable data bit rates are:
4. Following the last data bit of a valid reception, the Word
Gap timer samples the Null shift register every 10 input
clocks (every 80 clocks for low speed). If a Null is present,
the Word Gap counter is incremented. A Word Gap count of 3
enables the next reception.
DATA BIT RATE MAX
DATA BIT RATE MIN
ARINC word
matches
Enabled
label
Yes
Yes
Yes
No
No
No
X
X
X
CR6
0
0
0
1
1
1
1
1
1
Depending on the state of Control
HIGH SPEED
ARINC word
125K BPS
bits 10, 9
83K BPS
match
CR7,8
Yes
Yes
Yes
No
No
No
X
X
X
LOW SPEED
10.4K BPS
15.6K BPS
Ignore data
Ignore data
Ignore data
Ignore data
Ignore data
Load FIFO
Load FIFO
Load FIFO
Load FIFO
FIFO