hi-3588pqt Holt Integrated Circuits, Inc., hi-3588pqt Datasheet - Page 6

• Manufacturer Part Number: hi-3588pqt
• Description: Receiver With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
Once a valid ARINC word is loaded into the FIFO, the EOS signal
clocks the Data Ready flip-flop to a "1" and Status Register bit 0
(SR0) to a “0”. The SR0 bit remains low until the Receive FIFO is
empty. Each received ARINC word is retrieved via the SPI interface
using SPI instruction 08 hex to read a single word, or 09 hex to
empty the entire Receive FIFO.
Up to 32 ARINC words may be held in the Receive FIFO. Status
register bit 2 (SR2) goes high when the Receive FIFO is full.
Failure to unload the Receive FIFO when full causes additional
received valid ARINC words to overwrite Receive FIFO location 32.
16 or more ARINC words. SR1 may be interrogated by the system’s
external microprocessor, allowing a 16 word data retrieval routine
to be performed.
LABEL RECOGNITION
The user loads the 256-bit label look-up table to specify which 8-bit
incoming ARINC labels are captured by the receiver, and which are
discarded. Setting a “1” in the look-up table enables processing of
received ARINC words containing the corresponding label. A “0” in
the look-up table causes discard of received ARINC words
containing the label. The 256-bit look-up table is loaded using SPI
op codes 02 hex, 03 hex or 06 hex, as described in Table 1. After
the look-up table is initialized, set Control Register bit CR2 to
enable label recognition.
If label recognition is enabled, the receiver compares the label in
each new ARINC word against the stored look-up table. If a label
match is found, the received word is processed. If no match
A FIFO half-full flag (SR1) is high when the Receive FIFO contains
CONTROL BITS
CR2, CR6-8
RFLAG
ZEROS
ONES
NULL
CONTROL
LOAD
FIFO
EOS
LOOK-UP
256-BIT
LABEL
TABLE
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
/
COMPARE
DECODE
LABEL /
FIGURE 2.
32 BIT SHIFT REGISTER
HOLT INTEGRATED CIRCUITS
32 X 32
FIFO
RECEIVER BLOCK DIAGRAM
HI-3588
WORD GAP
6
BIT CLOCK
occurs, the new ARINC word is discarded and no indicators of
received ARINC data are presented.
READING THE LABEL LOOK-UP TABLE
The contents of the Label Look-up table may be read via the SPI
interface using instruction 0D hex as described in Table 1.
LINE RECEIVER INPUT PINS
The HI-3588 has two sets of Line Receiver input pins, RINA/B
and RINA/B-40. Only one pair may be used to connect to the
ARINC 429 bus. The unused pair must be left floating. The
RINA/B pins may be connected directly to the ARINC 429 bus.
The RINA/B-40 pins require external 40K ohm resistors in series
with each ARINC input. These do not affect the ARINC receiver
thresholds. By keeping excessive voltage outside the device, this
option is helpful in applications where lightning protection is re-
quired.
When using the RINA/B-40 pins, each side of the ARINC bus
must be connected through a 40K ohm series resistor in order for
the chip to detect the correct ARINC levels. The typical 10 Volt dif-
ferential signal is translated and input to a window comparator
and latch. The comparator levels are set so that with the external
40K ohm resistors, they are just below the standard 6.5 volt mini-
mum ARINC data threshold and just above the standard 2.5 volt
maximum ARINC null threshold.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.
START
DATA
CONTROL BITS
CR0, CR1
PARITY
CHECK
WORD GAP
SEQUENCE
DETECTION
CONTROL
ERROR
TIMER
32ND
BIT
SPI INTERFACE
END
ERROR
CLOCK
SEQUENCE
BIT CLOCK
COUNTER
OPTION
END OF
CLOCK
AND
BIT
CLOCK
ACLK
CS
SI
SO
SCK