scn68562 NXP Semiconductors, scn68562 Datasheet - Page 9

• Manufacturer Part Number: scn68562
• Description: Dual Universal Serial Communications Controller Duscc
• Manufacturer: NXP Semiconductors

1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For DC and functional testing, all inputs except X1/CLK swing between 0.8V and
3. Test conditions for outputs: C
4. This specification will impose maximum 68000 CPU CLK to 6MHz. Higher CPU CLK can be used if repeating bus cycles are not performed.
5. Execution of the valid command (after it is latched) requires three falling edges of X1 (see Figure 14).
6. In single address DMA mode write operation, data is latched by the falling edge of DTCN.
7. These values were not explicitly tested, they are guaranteed by design and characterization data.
8. These timings are from the falling edge of DTACKN (not CSN rising).
9. X1/CLK frequency must be at least four times the receiver serial data rate.
Philips Semiconductors
NOTES:
1995 May 01
Dual universal serial communications controller (DUSCC)
2.0V with a transition time of 20ns maximum. For X1/CLK, this swing is between 0.4V and 2.4V All time measurements are referenced at
input voltages of 0.4V and 2.4V for all inputs. Output levels are referenced at 1.2V and 2.0V, as appropriate.
except DTACKN whose R
NO.
NO.
42
43
44
FIGURE
FIGURE
16
16
16
DTACKN
A1–A6
D0–D7
R/WN
CSN Low to transmit DMA REQ negated
CSN Low to receive DONEN Low
CSN Low to receive DMA REQ negated
COMMAND
CSN
L
DTACKN
X1/CLK
= 820 to V
VALID
L
= 150pF, except open-drain outputs. Test condition for open-drain outputs: C
CC
RESETN
and C
2
4
8
L
Figure 4. Bus Timing (Read Cycle)
= 150pF to GND and DONEN which requires C
PARAMETER
PARAMETER
Figure 5. Command Timing
Figure 3. Reset Timing
12
11
1
9
SD00224
7
5
13
9
L
= 50pF to GND and R
3
Min
6
L
= 50pF to GND, R
LIMITS
SD00225
SD00226
14
Typ
SCN68562
L
Max
Product specification
400
300
400
= 1k to V
L
= 2.7k to V
UNIT
UNIT
CC
nS
nS
nS
.
CC