uaa3522hl NXP Semiconductors, uaa3522hl Datasheet - Page 9

• Manufacturer Part Number: uaa3522hl
• Description: Low Power Dual-band Gsm Transceiver With An Image Rejecting Front-end
• Manufacturer: NXP Semiconductors

Table 4 Register bit allocation
X = don’t care; MSB = Most Significant Bit; LSB = Least Significant Bit.
Notes
1. Bit LNA: 1 = LNA ON in RX mode; 0 = LNA OFF in RX mode.
2. Bits Q sign and I sign = polarity of offset at Q/I channel outputs: 0 = negative offset step (output A with respect to output B); 1 = positive offset step
3. Bit IF RD: 0 = frequency dividers programmed for GSM applications; 1 = frequency dividers programmed for DCS applications.
4. Bit IF VCO: 0 = IF LO buffer ON (external IF LO source connected); 1 = IF VCO ON (external IF LO source not connected).
5. Bit RF: 1 = RF section ON when RX mode is activated; 0 = RF section OFF when RX mode is activated.
6. This address must not be used. Data bits to be defined.
FIRST
MSB
BIT
13
X
X
X
X
(output A with respect to output B).
12
X
X
X
X
MSB
11
X
X
X
Q output offset adjust
10
X
X
X
X
9
X
X
IF RD
X
X
8
(3)
RF LO frequency divider ratio
For test purposes only
IF VCO
LNA
MSB
LSB
7
(1)
DATA BITS
(4)
Q sign
X
6
0
(2)
(6)
MSB
MSB
IF LO frequency divider ratio
5
0
RF
AGC amplifier gain (RX mode)
I output offset adjust
4
(5)
X
3
see Table 5
SYN ON
2
RX ON
LSB
1
I sign
TX ON
LSB
LSB
LSB
0
(2)
3
0
0
0
0
0
0
ADDRESS BITS
2
1
1
0
0
0
0
1
1
0
1
1
0
0
LAST
BIT
0
0
0
1
0
1
0