hi-8120j-85 Holt Integrated Circuits, Inc., hi-8120j-85 Datasheet - Page 2

• Manufacturer Part Number: hi-8120j-85
• Description: Cmos High Voltage Display Driver
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION
Whenever a Logic "0" is applied to the Chip Select (
input, one bit of data is clocked into the shift register from the
serial data input (DIN) with each negative transition of the
Clock (
will cause a parallel transfer of data from the shift register to
the data latch. If the Load (LD) input is held high while data
is clocked into the shift register, the latch will be transparent.
All four logic inputs are TTL compatible on the HI-8020 and
CMOS compatible on the HI-8120.
To display segments, a Logic "1" is stored in the appropriate
shift register bit position, and the segment output is out-of-
phase with the backplane.
The backplane output functions in 1 of 2 modes; externally
driven or self-oscillating. When the LCDØ input is externally
driven with the LCDØOPT input open circuit (Figure 2), the
backplane output will be in-phase with LCDØ. Utilizing the
self-oscillating mode, inputs LCDØ and LCDØOPT are tied
together and connected to an RC circuit (Figure 3).
A 150K
approximate backplane frequency of 100Hz. The
LCDØ/LCDØOPT oscillator frequency is divided by 256 to
determine the backplane output frequency. The resistor
value (R) must be at least 30K
operation.
For displays having a number of segments greater than 38,
two or more of the display drivers may be cascaded together
by connecting the serial data output (DOUT) from the first
driver, to the serial data input (DIN) of the following driver,
etc.(See Figures 2 & 3). Data out (DOUT) will change state
TIMING DIAGRAM
OUTPUT
INPUT
INPUT
INPUT
INPUT
DOUT
DIN
CL
CS
LD
CL
W
) input. A Logic "1" present at the Load (LD) input
resistor with a 470pF capacitor generates an
t
CSS
W
t
DS
VALID
for proper self-oscillator
VALID
t
DH
t
CSH
t
CL
HI-8020/HI-8120 Series
HOLT INTEGRATED CIRCUITS
t
CDO
CS
)
LCDØ
LCDØ
OPT
INTERNAL OSCILLATOR CIRCUIT
2
on the rising edge of the Clock (
and Chip Select (
other, respectively, between all cascaded display drivers.
VALID
VALID
t
LS
CS
) should be tied in common with each
t
CSL
t
Figure 1.
LW
t
LCS
CL
). Clock (
TO BACKPLANE
TRANSLATOR
AND DRIVER
VALID
C
CL
÷ 256
), Load (LD)
Q
R