hi-8583pqt Holt Integrated Circuits, Inc., hi-8583pqt Datasheet
hi-8583pqt
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hi-8583pqt Summary of contents
Page 1
... Pin Plastic Quad Flat Pack (PQFP) (See page 14 for additional pin configuration) HOLT INTEGRATED CIRCUITS www.holtic.com ARINC 429 System on a Chip (Top View N CWSTR 37 - ENTX HI-8582PQI 35 - TXBOUT HI-8582PQT 34 - TXAOUT & FFT HI-8583PQI 31 - HFT HI-8583PQT PL2 28 - PL1 27 - BD00 03/07 ...
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... Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. Transmitter FIFO Half Full Transmitter FIFO Full -9 ...
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... Unscramble ARINC data HI-8582, HI-8583 STATUS REGISTER The HI-8582/HI-8583 contain a 9-bit status register which can be interrogated to determine the status of the ARINC receivers, data FIFOs and transmitter. The contents of the status register are is pulsed low. The output on BD00 - BD08 when the SEL = 0 ...
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... Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the data bit time. For a Null in the word gap, three consecutive Nulls must be found in both the upper and lower bits of the sampling shift register ...
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... CR2-CR11, the received ARINC 32-bit word is then checked for correct decoding and label matching before being loaded into the receive FIFO. ARINC words which do not meet the necessary 9th and 10th ARINC bit or label matching are ignored and are not loaded into the receive FIFO. The following table describes this operation ...
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... PL2 the 31 bit word (or 32 bit word if CR4=0) in the next available position of the FIFO. If TX/R, the transmitter ready flag is high (FIFO empty), then words, each bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 32 positions are full, the FIFO ignores further attempts to load data ...
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... The parity generator counts the Ones in the 31-bit word. If control register bit CR12 is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. Setting CR4 to a Zero bypasses the parity generator, and allows 32 bits of data to be transmitted. ...
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... BIT 31 BIT 32 D D/R DON'T CARE SEL EN DATA BUS t ENDATA DATA BUS PL1 PL2 TX/R, HFT FFT , DATA BUS CWSTR HI-8582, HI-8583 DATA RATE - EXAMPLE PATTERN DATA DATA NULL NULL BIT 32 BIT 31 RECEIVER OPERATION t t SELEN t SELEN ENSEL t t ENEN D/REN t DATAEN ...
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... PL t CWSTR CWSTR EN1 or EN2 t CWHLD t CWSET DATA BUS Set CR1=1 Label #1 t ENDATA HI-8582, HI-8583 STATUS REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA CONTROL REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA LABEL MEMORY LOAD SEQUENCE Label #2 ...
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... TXBOUT) 10% one level BIT 32 RIN D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TXR ENTX TXAOUT TXBOUT HI-8582, HI-8583 TRANSMITTING DATA ARINC BIT ARINC BIT DATA DATA BIT 2 BIT 1 +5V -5V +5V - +10V 90 10% rx 90% ...
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... Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HI-8582, HI-8583 Power Dissipation at 25°C Plastic Quad Flat Pack ..................1.5 W, derate 10mW/ C Ceramic J-LEAD CERQUAD ...... 1.0 W, derate 7mW/ DC Current Drain per pin .............................................. ± ...
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... RIN1B, RIN2A to RIN2B GND Input Voltage Input Voltage Input Sink I IH Input Source I IL Input Voltage Input Voltage Input Sink I IH Input Source I IL NFD Pin One or zero V No load and magnitude at pin, ...
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... Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX LOW LINE DRIVER OUTPUT TIMING Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed Line driver transition differential times: (High Speed, control register CR13 = Logic 0) (Low Speed, control register CR13 = Logic 1) ...
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... ADDITIONAL HI-8582 / HI-8583 PIN CONFIGURATIONS BD15 - 16 BD14 - 17 BD13 - 18 BD12 - 19 BD11 - 20 ORDERING INFORMATION HI - 85xx HI-8582, HI-8583 FF1 - 8 HF1 - 9 D/ FF2 - 11 HF2 - 12 HI-8582CJI SEL - 13 HI-8582CJT EN1 - 14 & EN2 -15 HI-8583CJI HI-8583CJT 52 - Pin Cerquad J-lead (See page 1 for additional pin configuration) INPUT SERIES RESISTANCE ...
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... HI-8582 / HI-8583 PACKAGE DIMENSIONS 52-PIN J-LEAD CERQUAD 7 8 .019 .002 (.483 .051) 52-PIN PLASTIC QUAD FLAT PACK (PQFP) .520 BSC SQ (13.2) .063 (1.6) See Detail A .084 .013 ± (2.13 ± .32) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) ...