hi-8589pqt Holt Integrated Circuits, Inc., hi-8589pqt Datasheet - Page 6

• Manufacturer Part Number: hi-8589pqt
• Description: Transmitter With Line Driver And Dual Receivers
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
TIMING DIAGRAMS
LINE DRIVER OPERATION
The line driver in the HI-8581 and HI-8589 is designed to directly
drive the ARINC 429 bus. The two ARINC outputs (TXA(OUT) and
TXB(OUT)) provide a differential voltage to produce a +10 volt
One, a -10 volt Zero, and a 0 volt Null. Setting Control Register bit
13 to zero causes a slope of 1.5 s on the ARINC outputs. A one in
Control Register bit 13 causes a slope of 10 s. Timing is set by on-
chip resistor and capacitor and tested to be within ARINC require-
ments.
HI-8581 has 37.5 ohms whereas the HI-8589 has 10 ohms in
series with each line driver output. The HI-8589 is for applications
where additional external series resistance is required, such as
lightning protection.
REPEATER OPERATION
Repeater mode of operation allows a data word that has been
received by the HI-8581 or HI-8589 to be placed directly into its
FIFO for transmission. Repeater operation is similar to normal
receiver operation. In normal operation, either byte of a received
data word may be read from the receiver latches first by use of SEL
input. During repeater operation however, the lower byte of the
data word must be read first. This is necessary because, as the
data is being read, it is also being loaded into the FIFO and the
transmitter FIFO is always loaded with the lower byte of the data
word first. Signal flow for repeater operation is shown in the
Timing Diagrams section.
TXB(OUT)
TXA(OUT)
No additional hardware is required to control the slope.
DATA BUS
CWSTR
DATA
ARINC BIT
BIT 30
NULL
m
DATA
m
BIT 31
HOLT INTEGRATED CIRCUITS
DATA RATE - EXAMPLE PATTERN
NULL
LOADING CONTROL WORD
HI-8581, HI-8589
t
CWSTR
DATA
t
CWSET
The
BIT 32
VALID
6
NULL
HI-8581-10 and HI-8589-10
The “-10” versions of the HI-8581 and HI-8589 products require a
10 Kohm resistor to be placed in series with each ARINC input
without affecting the ARINC input thresholds. This option is
especially useful in applications where external lightning
protection is required.
Each ARINC input pin must be connected to the ARINC bus
through a 10 Kohm resistor in order for the chip to properly detect
the correct ARINC levels. The typical 10 volt differential signal is
translated and input to a window comparator and latch. The
comparator levels are set so that with the external 10 Kohm
resistors, they are just below the standard 6.5 volt minimum
ARINC data threshold and just above the 2.5 volt maximum
ARINC null threshold.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.
POWER SUPPLY SEQUENCING
The power supplies should be controlled to prevent large currents
during supply turn-on and turn-off. The recommended sequence
is V+ followed by Vcc, always ensuring that V+ is the most
positive supply. The V- supply is not critical and can be asserted
at any time.
MASTER RESET (
On a Master Reset data transmission and reception are
immediately terminated, all three FIFOs are cleared as are the
FIFO flags at the device pins and in the Status Register. The
Control Register is not affected by a Master Reset.
t
CWHLD
WORD GAP
MR
)
NEXT WORD
BIT 1