co661al-l Connect One Ltd., co661al-l Datasheet - Page 14

• Manufacturer Part Number: co661al-l
• Description: The Co661al-l Ichip Lan? Internet Controller? Is Part Of A Family Of Intelligent Peripheral Devices That Provides Internet Connectivity Solutions To A Myriad Of Embedded Devices
• Manufacturer: Connect One Ltd.

4 Hardware Interface
iChip LAN CO661AL-L may interface a host CPU in one of two methods: Serial or
Parallel. The actual interface depends on the state of the –SER/PAR pin.
4.1 Serial Host Interface
The host interface is a serial DTE interface. Speeds of 2400, 4800, 9600, 19200, 38400,
57600, 115200 and 230400 bps are supported in the following data format:
All host serial input signals (RXDH, -CTSH, -DSRH) are 5V tolerant.
4.2 Parallel Host Interface
In parallel interface mode, iChip LAN connects to a host CPU through a parallel interface
using a PAL (i.e., Altera “EPM7032AEC44”). The host parallel BUS may be an 80x86
(Intel) or a 68K (Motorola) BUS. With some small changes to the PAL, the user may
customize an interface to any other BUS architecture. iChip LAN is connected to the
interface PAL through the following signals:
Notes:
iChip LAN CO661AL-L Datasheet
•
• -RD:
• -WR:
•
• -PRES: Parallel reset. When LOW, generates a reset signal to the parallel
• -PERR: Parallel error. When LOW, indicates a parallel interface error.
• POBE: Parallel Output Buffer Empty. When HIGH, indicates that the output
• PIBF:
PCS:
D0-D7: Bi-directional data BUS.
1: When hardware flow control is enabled, the iChip LAN transmitter will add
2: Parallel interface mode will be available only from iChip LAN firmware version 801.
an additional stop bit.
Parity
None
Parallel chip select signal. When PCS is high, the PAL is selected.
When –RD is LOW, iChip LAN reads data from PAL.
When –WR is LOW, iChip LAN writes data to PAL.
interface.
buffer is empty and iChip LAN may send additional data to host. When
iChip LAN sends a data byte, this signal goes LOW until the host reads
the data.
Parallel Input Buffer Full. When HIGH, indicates that the input buffer is
full and iChip LAN may read a data byte from the host. When iChip
LAN reads the data byte, this signal goes LOW.
Data Length
(No. of Bits)
Table 4-1 Host Data Format
8
2
Stop Bits
No. of
1
1
Transmission
(No. of Bits)
Length
Hardware Interface
10
4-1