mh1020 Music Semiconductors, Inc., mh1020 Datasheet - Page 17

• Manufacturer Part Number: mh1020
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

devices (and assuming the Device Select registers are set
to FFFFH), all devices respond to that command write or
data write.
From then on the daisy chain remains locked in each
subsequent cycle as long as /EC is held LOW on the
falling edge of /E in the current cycle. When the daisy
chain
Highest-Priority Match device responds (See Case 6 of
Table 4). If, for example, all of the CAM memory
locations were empty, there would be no match, and /MF
would stay HIGH. Since none of the devices could then be
the Highest-Priority Match device, none respond to reads
or writes until the daisy chain is unlocked by taking /EC
HIGH and asserting /E for a cycle.
If there is a match between the data in the Comparand
register and one or more locations in memory, then only
the Highest-Priority Match device responds to any cycle,
such as an associated data or Status Register read. If there
is not a match, then a NOP with /EC HIGH needs to be
inserted before issuing any new instructions, such as Write
to Next Free Address instruction to learn the data. Since
Next Free operations are controlled by the /FI–/FF daisy
chain, only the device with the first empty location
responds. If an instruction is used to unlock the daisy
chain, it works only on the Highest-Priority Match device,
if one exists. If none exists, the instruction has no effect
except to unlock the daisy chain. To read the Status
registers of specific devices when there is no match
requires the use of the TCO DS command to set DS=PA of
each device. Single chip systems can tie /EC HIGH and
read the Status register or the /MA and /MM pins to
monitor match conditions, as the daisy chain lock-out
feature is not needed in this configuration. This removes
the need to insert a NOP in the case of a no-match.
When the Control register is set to Enhanced mode, you
can continue to write data to the Comparand register or
issue a Move to Next Free Address instruction without
first having to issue a NOP with /EC HIGH to unlock the
daisy chain after a Compare cycle with no match, as
indicated in cases 4 and 5 of Table 4 on page 11. In
Enhanced mode, data write cycles as well as command
write cycles are enabled in all devices even when /EC is
LOW. Exceptions are data writes, moves, or VBC
instructions involving HM, which occur only in the device
with the highest match; and data writes or move
instructions involving NF, which occur only in the device
with /FI LOW and /FF HIGH. Enhanced mode speeds up
system performance by eliminating the need to unlock the
daisy chain before Command or Data Write cycles.
Rev. 1
is
locked
in
Standard
mode,
only
the
17
Full Flag Cascading
The Full Flag daisy chain cascading has the following
three purposes:
•
•
•
The full flag logic causes only the device containing the
first empty location to respond to Next Free instructions
such as MOV NF,CR,V, which moves the contents of the
Comparand register to the first empty location in a string
of devices and sets that location Valid, making it available
for the next automatic compare. With devices connected as
in Figure 3 on page 7, the /FF output of the last device in a
string provides a full indication for the entire string.
IEEE 802.3/802.5 Format Mapping
To support the symmetrical mapping between the address
formats of IEEE 802.3 and IEEE 802.5, the MH provides a
bit translation facility. Formally expressed, the nth input
bit, D(n), maps to the xth output bit, Q(x), through the
following expressions:
Setting Control Register bit 10 and bit 9 selects whether to
persistently translate, or persistently not to translate, the
data written onto the 64-bit internal bus. The default
condition after a Reset command is not to translate the
incoming data. Figure 5 on page 9 shows the bit mapping
between the two formats.
Initializing the MH
Initialization of the MH is required to configure the
various registers on the device. Since a Control register
reset establishes the operating conditions shown in Table 3
on page 11, restoration of operating conditions better
suited for the application may be required after a reset,
whether using the Control Register reset, or the /RESET
pin. When the device powers up, the memory and registers
are in an unknown state, so the /RESET pin must be
asserted to place the device in a known state.
Setting Page Address Register Values
In a vertically cascaded system, the user must set the
individual Page Address registers to unique values by
using the Page Address initialization mechanism. Each
Page Address register must contain a unique value to
prevent bus contention. This process allows individual
device selection. The Page Address register initialization
works as follows: Writes to Page Address registers are
only active for devices with /FI LOW and /FF HIGH. At
Allow instructions that address Next Free locations to
operate globally
Provide a system wide Full flag
Allow the loading of the Page Address registers
during initialization using the SFF instruction
D(n) = Q(7–n) for 0 < n < 7,
D(n) = Q(23–n) for 8 < n < 15