mh2080 Music Semiconductors, Inc., mh2080 Datasheet - Page 6

• Manufacturer Part Number: mh2080
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

TCLK (JTAG Test Clock, Input)
The TCLK input is the Test Clock input. This pin is
internally pulled up.
TMS (JTAG Test Mode Select, Input)
The TMS input is the Test Mode Select input. This pin is
internally pulled up.
TDI (JTAG Test Data Input, Input)
The TDI input is the Test Data input. This pin is internally
pulled up.
TDO (JTAG Test Data Output, Output)
The TCLK output is the Test Data Output. This pin is
internally pulled up.
/RESET
MH2080 top view
/TRST
DQ16
DQ17 DQ18
DQ22 DQ23
DQ24 DQ25
DQ27 VCC
DQ28 DQ29
GND
/CS1
GND
VCC DQ20
DQ19
DQ21
DQ26
DQ30
DQ31
GND
/CS2
/OE
/AV
/VB
/W
/E
Figure 4: MH 2080 High density Leadless Array (HLA) pinout
DQ15
TCLK
GND
TMS TDI
DQ14
DQ12
DQ13
TDO
GND
VCC
AC0
DQ11
AC1
DQ10
AC2
DQ9
AC3
DQ8
VCC AC4
6
GND
DQ7
AC5
/TRST (JTAG Reset, Input)
The /TRST input is the Reset input, and serves to reset the
Test Access Port circuitry to its reset condition. This pin is
internally pulled up.
VDD, VSS (Positive Power Supply, Ground)
These pins are the main power supply connections to the
MH2080. VDD must be held at +3.3 Volts and ± 0.3 Volts
relative to the VSS pin, which is at 0 Volts, system
reference potential, for correct operation of the device.
Note: The TCLK, TMS, TDI, TDO, and /TRST lines are defined
in the IEEE Standard Test Access Port and Boundary-scan
Architecture IEEE Standard. 1149.1-1990 and IEEE Standard.
1149.1a-1993.
DQ6
AC6
DQ5
AC7
GND
DQ4
VCC
DQ3
AC9 AC10 AC11
AC8
DQ2
AC12
DQ0
DQ1
AA12
AA10 AA11
GND PA0
GND AA8
VCC AA4
GND
VCC
GND
PA2 PA3
PA1
AA9
AA7
AA5 AA6
AA3
AA2
AA0
/FF
/FI
GND
DSC
AA1
/MM
/MF
/MI
NC
Rev. 1.1a