mh2080 Music Semiconductors, Inc., mh2080 Datasheet - Page 25

• Manufacturer Part Number: mh2080
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

VALIDITY BIT CONTROL
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS
Description: Set the Validity bit LOW at the location
pointed to by the contents of the Address register. The
location is set valid and will enter into comparisons during
a Comparison cycle, and will not be written to during a
Write at Next Free Address cycle. DSC must be LOW.
Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH /AV: HIGH PA:AA: aaa Scope: S
Description: Reads the Validity bit at the location
addressed by the contents of the Address register onto
DQ0. When the validity value is LOW, the location is
valid; when the validity value is HIGH, the location is
empty. DQ31-1 will read as logical 0s. DSC must be
LOW.
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS
Description: Set the Validity bit HIGH at the location
pointed to by the contents of the Address register. The
location is set empty and will not enter into comparisons
during a Comparison cycle, and may be written to during a
Write at Next Free Address cycle. DSC must be LOW.
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: HPMA Scope: HPD
Description: Set the Validity bit HIGH at the
highest-priority matching location from the previous
Comparison cycle. The location is set empty and will not
enter into comparisons during a Comparison cycle, and
may be written to during a Write at Next Free Address
cycle. DSC must be LOW.
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: HPMA Scope: AS
Description: Set the Validity bit HIGH at all matching
locations from the previous Comparison cycle. The
locations are set empty and will not enter into comparisons
during a Comparison cycle, and will be written to during a
Write at Next Free Address cycle. DSC must be LOW.
Rev. 1.1a
Set Valid Indirect
SET V@[AR]
XXX XXX 100 000
Read Validity Indirect
RD V@[AR]
XXX XXX 100 000
Set Empty Indirect
RST V@[AR]
XXX XXX 100 001
Set Empty at Highest-Priority
Matching Location
RST V@[HPM]
XXX XXX 100 010
Set Empty at All Matching
Locations
RST V@[AML]
XXX XXX 100 011
25
INITIALIZATION
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: n/c Scope: NFD
Description: Writes DQ3-0 to the Page Address field of
the Configuration register, and sets the /FF LOW. This
control state is intended for sequential loading of Page
addresses in vertically cascaded systems that do not have
explicit lines controlling the /CS inputs to the individual
devices. DSC must be LOW.
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS
Description: Resets /FF HIGH. Used after sequentially
loading the PA fields with previous control state to set the
system back to empty. DSC must be LOW.
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: All 1s Scope: AS
Description: Resets the MH2080. DSC must be LOW.
ADDRESS REGISTER CONTROL
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS
Description: Increments the value held in the Address
register. Used for automatic sequencing through addresses
in the Memory array. DSC must be LOW.
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS
Description: Decrements the value held in the Address
register. Used for automatic sequencing through addresses
in the Memory array. DSC must be LOW.
Control State:
Mnemonic:
Description: Binary Op-Codes that are not documented
are reserved control states. The results of these control
states are undefined.
Reset Full Flag
Reset
Undefined Operations
Write Page Address to
Highest-Priority Empty Device;
Set Full
WR PA
XXX XXX 111 100
RST FF
XXX XXX 111 101
RST
XXX XXX 111 111
Increment Address Register
INC AR
XXX XXX 100 100
Decrement Address Register
DEC AR
XXX XXX 100 101
RESERVED