89hpes34h16 Integrated Device Technology, 89hpes34h16 Datasheet - Page 2

• Manufacturer Part Number: 89hpes34h16
• Description: 34-lane, 16-port Pcie System Interconnect Switch
• Manufacturer: Integrated Device Technology

Product Description
the most efficient I/O connectivity for applications requiring high
throughput, low latency, and simple board layout with a minimum
number of board layers. Each lane provides 2.5 Gbps of bandwidth in
both directions and is fully compliant with PCI Express Base specifica-
tion 1.1.
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers. The PES34H16 can operate either as a store and
forward switch or a cut-through switch and is designed to switch memory
and I/O transactions. It supports eight Traffic Classes (TCs) and two
Virtual Channels (VCs) with sophisticated resource management to
enable efficient switching and I/O connectivity.
SMBus Interface
provides full access to the configuration registers in the PES34H16,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configura-
tion register values of the PES34H16 to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
IDT 89HPES34H16 Data Sheet
Utilizing standard PCI Express interconnect, the PES34H16 provides
The PES34H16 is based on a flexible and efficient layered architec-
The PES34H16 contains two SMBus interfaces. The slave interface
Six pins make up each of the two SMBus interfaces. These pins
◆
◆
◆
◆
– Internal end-to-end parity protection on all TLPs ensures data
– Supports optional PCI Express Advanced Error Reporting
– Supports PCI Express Hot-Plug
– Supports Hot-Swap
Power Management
– Supports PCI Power Management Interface specification,
– Unused SerDes disabled
Testability and Debug Features
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Thirty-two General Purpose Input/Output pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with
1mm ball spacing
• Compatible with Hot-Plug I/O expanders used on PC
• Supports powerdown modes at the link level (L0, L0s, L1,
integrity even in systems that do not implement end-to-end
CRC (ECRC)
Revision 1.1 (PCI-PM)
motherboards
L2/L3 Ready and L3) and at the device level (D0, D3
hot
)
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master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
in a unified or split configuration. In the unified configuration, shown in
Figure 2(a), the master and slave SMBuses are tied together and the
PES34H16 acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES34H16 registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES34H16 may be configured to operate in a split configuration as
shown in Figure 2(b).
two independent buses and thus multi-master arbitration is never
required. The PES34H16 supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
As shown in Figure 2, the master and slave SMBuses may be used
In the split configuration, the master and slave SMBuses operate as
Bit
Table 1 Master and Slave SMBus Address Assignment
1
2
3
4
5
6
7
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
SSMBADDR[5]
Address
SMBus
Slave
0
1
1
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
April 16, 2008
Address
Master
SMBus
1
0
1