89hpes34h16 Integrated Device Technology, 89hpes34h16 Datasheet - Page 16

• Manufacturer Part Number: 89hpes34h16
• Description: 34-lane, 16-port Pcie System Interconnect Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES34H16 Data Sheet
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
JTAG
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST_N
1.
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
Signal
GPIO (asynchronous input)
GPIO
GPIO[31:0]
1
1.
are asynchronous.
2.
,
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they
The values for this symbol were determined by calculation, not by testing.
Signal
1
EXTCLK
Thigh_16a,
Symbol
Tpw_16d
Tper_16a
Tlow_16a
Tdz_16c
Thld_16b
Tsu_16b
Tdo_16c
Symbol
Tpw_13b
2
2
Table 12 JTAG AC Timing Characteristics
Table 11 GPIO AC Timing Characteristics
Figure 4 GPIO AC Timing Waveform
2
JTAG_TCK falling
JTAG_TCK rising
Reference
Reference
Edge
none
none
Edge
None
16 of 45
Tpw_13b
Min
50
Min
10.0
25.0
50.0
2.4
1.0
—
—
Max Unit
—
Max
25.0
20
20
—
—
—
—
ns
Reference
See Figure 4.
Diagram
Unit
Timing
ns
ns
ns
ns
ns
ns
ns
Referenc
See Figure 5.
Diagram
Timing
e
April 16, 2008