am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 88

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

CSR1: IADR[15:0]
Bit
31–16 RES
15–0 IADR[15:0]
CSR2: IADR[31:16]
Bit
31–16 RES
15–8
Name
Name
IADR[31:24] If SSIZE32 is set (BCR20, bit 8),
initialization
completed.
INIT is set by writing a “1”. Writing
a “0” has no effect. INIT is cleared
by H_RESET, S_RESET or by
setting the STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Lower 16 bits of the address of
the Initialization Block. Bit loca-
tions 1 and 0 must both be ZERO
to align the initialization block to a
double-word boundary, regard-
less of the value of SSIZE32
(BCR20/CSR58, bit 8).
This register is aliased with
CSR16.
Read/Write
when the STOP bit in CSR0 is
set. Unaffected by H_RESET or
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
then the IADR[31:24] bits will be
used strictly as the upper 8 bits of
the initialization block address.
However, if SSIZE32 is reset
(BCR20,
IADR[31:24] bits will be used to
generate the upper 8 bits of all
bus mastering addresses, as re-
quired for a 32 bit address bus.
Note that the 16-bit software
structures
SSIZE32=0 setting will yield only
24 bits of address for PCnet-PCI
bus master accesses, while the
32-bit hardware for which the
PCnet-PCI controller is intended
will require 32 bits of address.
Therefore,
SSIZE32=0, the IADR[31:24] bits
will be appended to the 24-bit in-
itialization address, to each
24-bit descriptor base address
and to each beginning
buffer address in order to form
complete 32-bit addresses. The
upper 8 bits that exist in the de-
scriptor address registers and
bit
specified
accessible
sequence
8),
then
whenever
P R E L I M I N A R Y
by
24-bit
only
has
the
Am79C970
the
7–0 IADR[23:16]
CSR3: Interrupt Masks and Deferral Control
Bit
31–16 RES
15
14
13
12
BABLM
MISSM
Name
RES
RES
the buffer address registers
which are stored on board the
PCnet-PCI controller will be
overwritten with the IADR[31:24]
value, so that CSR accesses to
these registers will show the 32
bit address that includes the ap-
pended field.
If SSIZE32=1, then software will
provide 32-bit pointer values for
all of the shared software struc-
tures – i.e. descriptor bases and
buffer addresses, and therefore,
IADR[31:24] will not be written to
the upper 8 bits of any of these
resources, but it will be used as
the upper 8 bits of the initializa-
tion address.
This register is aliased with
CSR17.
Read/Write
when the STOP bit in CSR0 is
set. Unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Bits 23 through 16 of the address
of the Initialization Block. When-
ever this register is written,
CSR17 is updated with CSR2’s
contents.
Read/Write
when the STOP bit in CSR0 is
set. Unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved location. Read and
written as ZERO.
Babble Mask. If BABLM is set,
the BABL bit in CSR0 will be
masked and unable to set INTR
flag in CSR0.
Read/Write accessible always.
BABLM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Reserved location. Read and
written as ZERO.
Missed Frame Mask. If MISSM is
set, the MISS bit in CSR0 will be
masked and unable to set INTR
flag in CSR0.
Read/Write accessible always.
MISSM is cleared by H_RESET
accessible
accessible
AMD
1-955
only
only