am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 39

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

It is not necessary for the software to insure that the
buffer address pointer contained in descriptor word 0
matches the address restrictions given in the table. If the
buffer pointer does not meet the conditions set forth in
the table, then the PCnet-PCI controller will simply post-
pone the start of linear bursting until enough non-burst
FIFO DMA transfers have been performed to bring the
current working buffer pointer value to a valid linear
burst starting address. This operation is referred to as
aligning the buffer address to a valid linear burst starting
address. Once this has been done, the PCnet-PCI con-
troller will recognize that the address for the current ac-
cess is a valid linear burst starting address, and it will
automatically begin to perform linear burst accesses at
that time, provided of course that the software has en-
abled the linear burst mode.
Note that if the software would provide only valid linear
burst starting addresses in the buffer pointer, then the
PCnet-PCI controller could avoid performing the align-
ment operation. It would begin linear burst accesses on
the very first of the buffer transfers thereby allowing a
slight gain in bus bandwidth efficiency.
1-906
AMD
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled by the PCnet-PCI controller.
2
3
0110
n0Ch
Figure 16. Burst Alignment
4
P R E L I M I N A R Y
PAR
Am79C970
5
0000
DATA
Linear Burst DMA Address Alignment
Linear bursting may begin during a bus mastership pe-
riod which was initially performing only non-burst
operations. A change from non-burst operation to linear
bursting will normally occur during linear burst DMA ad-
dress alignment operations.
If the PCnet-PCI controller is programmed for burst
mode (i.e. BREADE and/or BWRITE bits of BCR18 are
set to ONE), and the PCnet-PCI controller requests the
bus, but the starting address of the first transaction does
not meet the conditions as specified in the table above,
then the PCnet-PCI controller will perform non-burst ac-
cesses until it arrives at an address that does meet the
conditions described in the table. At that time, and with-
out releasing the bus, the PCnet-PCI controller will in-
voke the linear burst mode.
Figure 16 shows an example of a linear burst DMA align-
ment operation being performed. The first access to the
transmit buffer is in non-burst mode, because the cur-
rent address does not align with a linear burst boundary.
The PCnet-PCI controller switches to burst mode begin-
ning with the second transfer. REQ stays asserted dur-
ing all transfers.
6
PAR
7
1110
n10h
8
PAR
9
0000
DATA
10
DATA
PAR
18220C-18
11