am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 101

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

7–0 SWSTYLE
1-968
AMD
Initialization Block and Transmit
and Receive descriptor bit maps
are affected. When cleared, this
bit indicates that the PCnet-PCI
controller
(PCnet-ISA) software structures.
Note: Regardless of the setting
of SSIZE32, the Initialization
Block must always begin on a
double-word boundary.
The value of SSIZE32 is deter-
mined by the PCnet-PCI control-
ler. SSIZE32 is read only by the
host.
The PCnet-PCI controller uses
the setting of the Software Style
register (BCR20, bits 7-0/CSR58
bits 7-0) to determine the value
for this bit. SSIZE32 is cleared by
H_RESET and is not affected by
S_RESET or STOP.
If SSIZE32 is reset, then bits
IADR[31–24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32 bit address
bus during master accesses initi-
ated by the PCnet-PCI controller.
This action is required, since the
16-bit software structures speci-
fied by the SSIZE32=0 setting
will yield only 24 bits of address
for PCnet-PCI controller bus
master accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to the PCnet-PCI controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the PCnet-PCI
controller for performing master
accesses.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
Note that the setting of the
SSIZE32 bit has no effect on the
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit.
Software Style register. The
value in this register determines
the style of I/O and memory re-
sources that are used by the
PCnet-PCI controller. The Soft-
ware Style selection will affect
the interpretation of a few bits
within the CSR space and the
utilizes
Am79C960
P R E L I M I N A R Y
Am79C970
CSR59: IR Register
Bit
31–16 RES
15–0 IRREG
SWSTYLE
All other
combs.
[7:0]
00h
01h
02h
Name
LANCE/
PCnet-
PCnet-
ILACC
Name PCNET SSIZE32 Interpretations
Style
Res.
ISA
PCI
Undef.
CSR-
1
0
1
width of the descriptors and
initialization block. Specifically:
All PCnet-PCI controller CSR
bits and BCR bits and all descrip-
tor, buffer and initialization block
entries not cited in the table
above are unaffected by the Soft-
ware Style selection and are
therefore always fully functional
as specified in the CSR and BCR
sections.
Read/write accessible only when
STOP bit is set.
The SWSTLYE register will con-
tain the value 00h following
H_RESET or S_RESET and will
be unaffected by STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. After H_RE-
SET, the value in this register will
be 0105h. The settings of this
register will have no effect on any
PCnet-PCI controller function.
This register always contains the
same value. It is not writeable.
Read accessible only when
STOP bit is set.
Undef.
0
1
1
Altered Bit
ALL CSR4 bits will
function as defined in the
CSR4 section.
TMD1[29] functions as
ADD_FCS
CSR4[9:8], CSR4[5:4]
and CSR4[1:0] will have
no function, but will be
writeable and readable.
CSR4[15:10], CSR4[7:6]
and CSR4[3:2] will
function as defined in the
CSR4 section.
TMD1[29] becomes
NO_FCS.
ALL CSR4 bits will
function as defined in the
CSR4 section.
TMD1[29] functions as
ADD_FCS
Undef.