zl50211 Zarlink Semiconductor, zl50211 Datasheet - Page 8

• Manufacturer Part Number: zl50211
• Description: 256 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

TDI1,TDI2,TDI3,TDI4,
TDI5,TDI6,TDI7,TDI8
TDO1,TDO2,TDO3,
TDO4,TDO5,TDO6
IRQ1, IRQ2, IRQ3,
Extra Device Pins
IRQ4, IRQ5, IRQ6,
PLLV
Signal Name
TDO7,TDO8
IRQ7, IRQ8
PLLV
PLLV
TRST
DD2
TMS
TCK
SS1
SS2
= 1.8V
Signals
Signals
Signals
Signal
Signal
Signal
Signal
Power
Power
JTAG
JTAG
JTAG
JTAG
JTAG
Type
User
PLL
PLL
-
J2, AH1,AG3,AF22,
AJ3,AH20,F27,H27
AK13,AH14,U3,V2,
AK3,AK24,J28,K28
AJ6,AG23,L30,L29
C25,AF26,H1,W4,
W3,E15,V4,AK16,
N4,AJ26,N3,AK5,
C13,V3,A12,B13,
K1,AK23,L2,AK2,
AK15,AK14,D13,
L1,AJ22,L4,AH4,
AG2,AE26,D22,
AF3,AF27,D24,
H3,V1,H4,AE3,
J3,W2,H2,AF4,
D25,E27,AF21
BGA Ball #
C24, AE27
AJ14
Zarlink Semiconductor Inc.
JTAG SIGNAL PINS
D6
D7
K2
PLL SIGNAL PINS
ZL50211
8
Interrupt Request (Open Drain Output). These
outputs go low when an interrupt occurs in any
channel. Each IRQ returns high when all the interrupts
have been read from the Interrupt FIFO Register of
respective EVP. A pull-up resistor (1 K typical) is
required at these outputs.
normal operation.
Test Mode Select (3.3 V Input). JTAG signal that
controls the state transitions of the TAP controller. This
pin is pulled high by an internal pull-up when not
driven. This signal is connected to all processors.
Test Clock (3.3 V Input). Provides the clock to the
JTAG test logic.This signal is connected to all
processors.
Test Reset (3.3 V Input). Asynchronously initializes
the JTAG TAP controller by putting it in the Test-Logic-
Reset state. This pin should be pulsed low on power-
up or held low, to ensure that all the EVP’s are in the
normal functional mode. This pin is pulled by an
internal pull-down when not driven. This signal is
connected to all EVP’s.
Test Serial Data In (3.3 V Input). JTAG serial test
instructions and data are shifted in on these pins.
These pins are pulled high by an internal pull-up when
not driven.
Test Serial Data Out (Output). JTAG serial data is
outputted on these pins on the falling edge of TCK.
These pins are held in high impedance state when
JTAG scan is not enabled.
PLL Power Supply. Must be connected to PLLV
1.8V.
PLL Ground. Must be connected to VSS.
No connection. The ball pins must be left open for
Signal Description
Data Sheet
DD2
=