zl50211 Zarlink Semiconductor, zl50211 Datasheet - Page 11

• Manufacturer Part Number: zl50211
• Description: 256 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk
Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the
DTDT is set internally to 0.5625 (-5 dB).
In some applications the return loss can be higher or lower than 6 dB. The EVP allows the user to change the
detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value
into the DTDT register.
The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:
where 0 < DTDT
Example:For DTDT = 0.5625 (-5 dB), the hexadecimal value becomes
1.3
Integrated into the EVP is a Path Change Detector. This permits fast reconvergence when a major change occurs
in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence is
achieved, but at a much slower speed.
The Path Change Detector is activated by setting the PathDet bit in Control Register 3 to “1”. An optional path
clearing feature can be enabled by setting the PathClr bit in Control Register 3 to “1”. With path clearing turned on,
the existing echo channel estimate will also be cleared (i.e., the adaptive filter will be filled with zeroes) upon
detection of a major path change.
1.4
After echo cancellation, there is always a small amount of residual echo which may still be audible. The EVP uses
Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the Adaptive
Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal
as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be
calculated by the following equation:
where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed
in dBm0. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the
following equation:
where 0 < NLPTHR
When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal
by an additional 30 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a
spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the
perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP.
The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2.
The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register 1. It should be noted
that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.
Path Change Detector
Non-Linear Processor (NLP)
(dec)
(dec)
< 1
< 1
NLPTHR
DTDT
TSUP = Lrin + 20log
(hex)
(hex)
Zarlink Semiconductor Inc.
= hex(DTDT
= hex(NLPTHR
ZL50211
11
10
(dec)
(NLPTHR)
(dec)
* 32768)
* 32768)
hex(
0.5625 * 32768
)
= 4800
hex
Data Sheet