zl50211 Zarlink Semiconductor, zl50211 Datasheet
zl50211
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zl50211 Summary of contents
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... Features • ZL50211 has eight Echo Voice Processors in a single BGA package. This single device provides 256 channels of 64 msec echo cancellation or 128 channels at 128 msec echo cancellation • Each Echo Voice Processor has the capability of cancelling echo over 32 channels • ...
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... ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation. This provides 256 channels of 64 milliseconds to 128 channels of 128 milliseconds echo cancellation or any combination of the two configurations. The ZL50211 supports ITU-T G.165 and G.164 tone disable requirements. ...
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... Offset nulling of all PCM channels • 10 MHz or 20 MHz master clock operation • 3.3 V pads and 1.8 V Logic core operation with 5-Volt tolerant inputs • IEEE-1149.1 (JTAG) Test Access Port ZL50211 3 Zarlink Semiconductor Inc. Data Sheet ...
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... ZL50211 ZL50211GB BGA BALL GRID ARRAY Figure 3 - 535 Ball BGA Ball Grid Array 4 Zarlink Semiconductor Inc. Data Sheet ...
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... VSS Power TE1, TE2, TE3, TE4, TE5, TE6, Test Mode TE7, TE8 Pins OUTPUT Test TEST PINS pins ZL50211 BGA Ball # AC5,AC26,AC27,AD26,AD5,AE5,AF12,AF13,AF1 4,AF17,AF18,AF19,AF24,AF6,AF7,AF8,AG24,AH 24,E13,E14,E17,E18,E19,E23,E24,E25,E6,E7,E8, F5,G26,G27,G5,H26,H5,M26,M5,N26,N5,P26,P27 , P4,P5,U26,U27,U4,U5,V26,V5,W26,W5 AA26,AA28,AA3,AA5,AB26,AB28,AB3,AB5,AF11, AF20,AG10,AG21,AG22,AH10,AH11,AH22,AJ15, AJ16,AJ9,AK9,C10,C11,C22,C23,C9,D10,D23,D9, E11,E20,E21,E22,J26,J27,J4,J5,K26,K27,K3,K5, L26,L27,L3,L5,Y26, Y27,Y3,Y5 ...
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... RESET7, RESET8 Rin1,Rin2,Rin3, User Rin4,Rin5,Rin6, Signals Rin7,Rin8 Sin1,Sin2,Sin3,Sin4, User Sin5,Sin6,Sin7,Sin8 Signals ZL50211 BGA Ball # A27,D5,A25,A26,A24,B24,A28 C14, D14 BGA Ball # User Signal Pins AK7,AJ8,AK8, Data Bus (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor AJ27,AK29,AJ28, AH27, AJ30 port. They are connected to all the EVP’ ...
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... User C4i Signal User Signal Fsel User MCLK Signal ZL50211 BGA Ball # A5,V30,A6,AH7, Receive PCM Signal Outputs (Output). Port 2 TDM AG8,V28,C26,C30 data output streams. Each Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. B7,W27,A7,AH8, Send PCM Signal Outputs (Output). Port 1 TDM AF9,W30,C29,D30 data output streams ...
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... Power PLLV PLL SS1 PLLV Power SS2 ZL50211 BGA Ball # N4,AJ26,N3,AK5, Interrupt Request (Open Drain Output). These AJ6,AG23,L30,L29 outputs go low when an interrupt occurs in any channel. Each IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register of respective EVP ...
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... AT1, AT2, AT3, AT4, PLL Test AT5, AT6, AT7, AT8 Signals The following description applies to a single EVP (Echo Voice Processor). Note that the ZL50211 contains eight EVP’s. 1.0 Single Echo Voice Processor (EVP) Description Each single Echo Voice Processor (EVP) contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers, Echo Canceller A (ECA) and Echo Canceller B (ECB) ...
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... During these periods, the adaptation process is slowed down but it is not halted. The slow convergence speed is set using the Slow sub-register in Control Register 4. During slow convergence, the adaptation speed is Slow reduced by a factor of 2 relative to normal convergence for non-zero values of Slow. If Slow equals zero, adaptation is halted completely. ZL50211 Non-Linear Offset Σ Processor Null ...
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... The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2. The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register 1. It should be noted that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled. ZL50211 DTDT = hex(DTDT ...
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... The G.164 recommendation defines the disable tone as a 2100 Hz (+21 Hz) sine wave with a power level between 0 to -31 dBm0. If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone Detector will trigger. ZL50211 Register or Bit(s) NLPSel (Control Register 3) NLRun1 (Control Register 3) ...
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... When narrow band signals are detected, adaptation is halted but the echo canceller continues to cancel echo. The NBSD will be active regardless of the EVP functional state. However the NBSD can be disabled by setting the NBDis bit to “1” in Control Register 2. ZL50211 Tone Detector ECA ...
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... The ZL50211 has been certified G.168 (1997), (2000) and (2002) compliant in all 64 ms cancellation modes (i.e. Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester. The ZL50211 has also been tested for G.168 compliance and all voice quality tests at AT&T Labs. The ZL50211 was classified as “carrier grade” echo canceller. ...
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... Canceller A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 16 groups of 2 cancellers that can be configured into Back-to-Back. Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a transmission device or between two codecs for echo control on analog trunks. ZL50211 channel ...
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... Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2, causes quiet code to be transmitted on Sout. In Extended Delay and in Back-to-Back configurations, MuteR and MuteS bits of Echo Canceller B must always be “0”. Refer to Figure 4 and to Control Register 2 for bit description. ZL50211 channel A Sin + ...
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... Serial Data Interface Timing The ZL50211 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz. The input and output data rate of the ST-BUS and GCI bus is 2.048 Mb/s. The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The EVP automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI ...
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... Figure 10 shows the memory map of the control/status register blocks for all echo cancellers of the EVP. When Extended Delay or Back-to-Back configuration is selected, Control Register 1 of ECA and ECB and Control Register 2 of the selected group of echo cancellers require special care. Refer to the EVP Register description section. ZL50211 Base Address + MS ...
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... Back-to-Back Configuration For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries quiet code. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B (Channel 11) will carry quiet code. ZL50211 Channels Group 0, 1 ...
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... Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section for description. The typical power consumption can be calculated with the following equation: where 0 ≤ Nb_of_groups ≤ 16. ZL50211 0000h --> Channel 0, ECA Ctrl/Stat Registers Channel 1, ECB Ctrl/Stat Registers 0020h --> ...
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... DD1 • Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a ZL50211 21 Zarlink Semiconductor Inc. Data Sheet ...
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... The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO. • Device Identification register The Device Identification register provides access to the following encoded information: device version number, part number and manufacturer's name. ZL50211 22 Zarlink Semiconductor Inc. Data Sheet . ...
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... T 10 Output Pin Capacitance S † Characteristics are over recommended operating conditions unless otherwise stated ° ‡ Typical figures are =3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD1 ZL50211 Symbol V DD_IO ) V DD_CORE ...
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... Master Clock Low 3 Master Clock High † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25° 3.3 V and for design aid only: not guaranteed and not subject to production testing DD1 ZL50211 Sym. Level V 0.5V TT DD1 V 0 ...
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... Characteristics are over recommended operating conditions unless otherwise stated ° ‡ Typical figures are 3.3 V and for design aid only: not guaranteed and not subject to production testing DD1 F0i t FPS C4i Rout/Sout Bit 0, Channel 31 Rin/Sin Bit 0, Channel 31 ZL50211 ‡ Sym. Min. Typ CSS t 0 RWS t 0 ADS ...
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... SOD Sout/Rout Bit 7, Channel 31 Bit 0, Channel 0 t SIS Sin/Rin Bit 7, Channel 31 Bit 0, Channel 0 Figure 12 - GCI Interface Timing at 2.048 Mb/s ODE Sout/Rout Figure 13 - Output Driver Enable (ODE) MCLK ZL50211 Bit 1, Channel 0 Bit 2, Channel 0 t SIH Bit 1, Channel 0 Bit 2, Channel ...
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... DS CS R/W A0-A12 D0-D7 READ D0-D7 WRITE DTA IRQ Figure 15 - Motorola Non-Multiplexed Bus Timing ZL50211 t CSS t RWS t ADS VALID ADDRESS t DDR VALID READ DATA t DSW VALID WRITE DATA t AKD t IRD 27 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH DHR V TT ...
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... When low, the echo canceller dynamically adapts to the echo path characteristics. 1 Bits marked as “1” or “0” are reserved bits and should be written as indicated. 0 Control Register 1 (Echo Canceller B) Bit reserved bit and should be written “0”. ZL50211 R/W Address: 00 hex Bit 5 Bit 4 ...
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... When high, data on Rout is muted to quiet code. When low, Rout carries active code. Note: In order to correctly write to Control Register 1 and 2 of ECB necessary to write the data twice to the register, one immediately after another. The two writes must be separated by at least 350 ns and no more than 20 us. ZL50211 ECA: Control Register 2 ECB: Control Register 2 ...
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... ECB: Decay Step Size Control Register (SSC) Bit 7 Bit 6 Bit Note: Bits marked with “0” are reserved bits and should be written “0” ZL50211 ECA: Status Register ECB: Status Register Bit 4 Bit 3 Bit 2 Reserve Reserve Reserve ECA: Flat Delay Register (FD) ...
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... SS taps (see SSC Length (512 or 1024) - [Decay Step Number (NS For example and SSC 7-0 4 512 - [4 x (4x2 )] = 256 taps for a filter length of 512 taps. ZL50211 FIR Filter Length (512 or 1024 taps) Figure 16 - The MU Profile x 8 taps. For example then MU=2 7-0 is: 0 ≤ FD 7-0 7-0 is zero ...
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... Table 5 below is the same Table shown on page 9. Feature NLP Selection Reject uncancelled echo as noise Reject double-talk as noise Noise level estimator ramping scheme Noise level ramping rate Noise level scaling ZL50211 ECA: Control Register 3 ECB: Control Register 3 Bit 4 Bit 3 RingClr Reserve Functional Description of Register Bits Register or Bit(s) ...
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... Noise level estimator ramping rate. When InjCtrl = 1, a lower value will give faster ramping. When InjCtrl = 0, a higher value will give faster ramping. The default value of 5 G.168 compliance with InjCtrl = 1. A value of C ZL50211 ECA: Control Register 4 ECB: Control Register 4 ...
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... These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. ZL50211 Bit 4 Bit 3 ...
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... DTDT7 DTDT6 DTDT5 This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s complement linear value defaults to 4800 The high byte is in Register 2 and the low byte is in Register 1. ZL50211 Bit 4 Bit 3 EP12 EP11 Bit 4 Bit 3 ...
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... MU7 MU6 MU5 Functional Description of Register Bits This register allows the user to program the level of MU bit 2’s complement value which defaults to 4000 = 1.0 The maximum value is 7FFF hex is in Register 1. ZL50211 (NLPTHR) (NLPTHR) Bit 4 Bit 3 Bit 2 NLP12 NLP11 NLP10 ...
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... Note that the -12 dB PAD bit in Control Register 1 provides attenuation in the Rin to Rout path, and will override the settings in Gains. ZL50211 ECA: Gains Register 2 ECB: Gains Register 2 Bit 4 Bit 3 Bit 2 Rin0 0 Rout2 ECA: Gains Register 1 ...
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... Address+00 to Base Address+3F hex Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. ZL50211 R/W Address: 400 Bit 4 Bit 3 Bit 2 MTDBI ...
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... Address+00 to Base Address+3F hex coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. ZL50211 hex Bit 4 Bit 3 MTDBI MTDAI Functional Description of Register Bits ...
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... Test IRQ: Useful for the application engineer to verify the interrupt service routine. When high, any change to MTDBI and MTDAI bits of the Main Control Register will cause an interrupt and its corresponding channel number will be available from the Interrupt FIFO Register. When low, normal operation is selected. ZL50211 Interrupt FIFO Register R/W Address: 410 Bit 4 ...
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