zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 75

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zl50416

Manufacturer Part Number
zl50416
Description
Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet

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13.9
13.9.1
I
13.9.2
I
Accessed by CPU, serial interface and I
13.9.3
I
Accessed by CPU, serial interface and I
2
2
2
C Address h0AA; CPU Address:h500
C Address h0AB; CPU Address:h501
C Address h0AC; CPU Address:h502
(Group 5 Address) Buffer Control/QOS Group
FCBAT – FCB Aging Timer
QOSC – QOS Control
FCR – Flooding Control Register
Bit [7:0]:
Bit [0]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
7
Tos-d
7
Tos
7
QoS frame lost is OK. Priority will be available for flow control enabled source only
when this bit is set (Default 0)
Per VLAN Multicast Flow Control (Default 0)
Select processor multicast queue size
Select TOS bits for Priority (Default 0)
Select TOS bits for Drop priority(Default 0)
- 0 – Disable
- 1 – Enable
- 0 = 16 entries
- 1 = 64 entries
- 0 – Use TOS [4:2] bits to map the transmit priority
- 1 – Use TOS [7:5] bits to map the transmit priority
- 0 – Use TOS [4:2] bits to map the drop priority
- 1 – Use TOS [7:5] bits to map the drop priority
6
Tos-p
6
TimeBase
FCB Aging time. Unit of 1ms. (Default FF)
This is for buffer aging control. It is used to configure the buffer aging
time. This function can be enabled/disabled through bootstrap pin. It
is not suggested to use this function for normal operation.
5
PMCQ
FCBAT
2
2
C (R/W)
C (R/W)
4
VF1c
4
Zarlink Semiconductor Inc.
ZL50416
3
3
U2MR
75
1
L
0
0
0
Data Sheet

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