zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 14

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

2.3
2.3.1
The ZL50416 has many programmable parameters, covering such functions as QoS weights, VLAN control, and
port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters.
The parameters are contained in 8-bit configuration registers. The ZL50416 allows indirect access to these
registers, as follows:
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In summary, access to the many internal registers is carried out simply by directly accessing only three registers –
two registers to indicate the address of the desired parameter, and one register to read or write a value. Of course,
because there is only one bus master, there can never be any conflict between reading and writing the
configuration registers.
2.3.2
The CPU interface is also responsible for receiving and transmitting standard Ethernet frames to and from the CPU.
To transmit a frame from the CPU:
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To receive a frame into the CPU:
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In summary, receiving and transmitting frames to and from the CPU is a simple process that uses one direct access
register only.
2.3.3
In addition to standard Ethernet frames described in the preceding section, the CPU is also called upon to handle
special “Control frames,” generated by the ZL50416 and sent to the CPU. These proprietary frames are related to
such tasks as statistics collection, MAC address learning, and aging, etc… All Control frames are up to 40 bytes
long. Transmitting and receiving these frames is similar to transmitting and receiving Ethernet frames, except that
the register accessed is the “Control frame data” register (address 111).
Specifically, there are eight types of control frames generated by the CPU and sent to the ZL50416:
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If operating in 8 bits-interface mode, two “index” registers (addresses 000 and 001) need to be written, to
indicate the desired 8-bit register address. In 16-bit mode, only one register (address 000) needs to be
written for the desired 16-bit register address.
To indirectly configure the register addressed by the two index registers, a “configure data” register (address
010) must be written with the desired 8-bit data.
Similarly, to read the value in the register addressed by the two index registers, the “configure data” register
can now simply be read.
The CPU writes a “data frame” register (address 011) with the data it wants to transmit (minimum 64 bytes).
After writing all the data, it then writes the frame size, destination port number, and frame status.
The ZL50416 forwards the Ethernet frame to the desired destination port, no longer distinguishing the fact
that the frame originated from the CPU.
The CPU receives an interrupt when an Ethernet frame is available to be received.
Frame information arrives first in the data frame register. This includes source port number, frame size, and
VLAN tag.
The actual data follows the frame information. The CPU uses the frame size information to read the frame
out.
Memory read request
Memory write request
Register Configuration, Frame Transmission, and Frame Reception
Register Configuration
Rx/Tx of Standard Ethernet Frames
Control Frames
Zarlink Semiconductor Inc.
ZL50416
14
Data Sheet