zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 12

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

1.0
1.1
The FDB interface supports SBRAM memory at 100 MHz. To ensure a non-blocking switch, one memory domain
with a 64 bit wide memory bus is required. At 100 MHz, the aggregate memory bandwidth is 6.4 Gbps, which is
enough to support 16 10/100 Mbps.
The Switching Database is also located in the external SRAM; it is used for storing MAC addresses and their
physical port number.
1.2
The 10/100 Media Access Control module provides the necessary buffers and control interface between the Frame
Engine (FE) and the external physical device (PHY). The ZL50416 has two interfaces, RMII or Serial (only for 10M).
The 10/100 MAC of the ZL50416 device meets the IEEE 802.3 specification. It is able to operate in either Half or
Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon
collision for up to 16 total transmissions. The PHY addresses for 16 10/100 MAC are from 08h to 17h.
1.3
One extra port is dedicated to the CPU via the CPU interface module. The CPU interface utilizes a 16/8-bit bus in
managed mode (Bootstrap TSTOUT6 makes the selection). It also supports a serial and an I
provides an easy way to configure the system if unmanaged.
1.4
The CPU can send a control frame to access or configure the internal network management database. The
Management Module decodes the control frame and executes the functions requested by the CPU.
1.5
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, sent to the
search engine, to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch
response from the search engine, the frame engine performs transmission scheduling based on the frame’s priority.
The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
1.6
The Search Engine resolves the frame’s destination port or ports according to the destination MAC address (L2) or
IP multicast address (IP multicast packet) by searching the database. It also performs MAC learning, priority
assignment, and trunking functions.
1.7
The LED interface provides a serial interface for carrying 16 port status signals.
1.8
Several internal tables are required and are described as follows:
•
Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame
stored in the FDB, e.g. frame size, read/write pointer, transmission priority, etc.
Frame Data Buffer (FDB) Interfaces
10/100 MAC Module (RMAC)
CPU Interface Module
Management Module
Frame Engine
Search Engine
LED Interface
Internal Memory
Block Functionality
Zarlink Semiconductor Inc.
ZL50416
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2
C interface, which
Data Sheet