zl50418 Zarlink Semiconductor, zl50418 Datasheet - Page 79
zl50418
Manufacturer Part Number
zl50418
Description
Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50418.pdf
(163 pages)
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14.7.3
CPU Address:h302
Accessed by CPU
Bit [7:0] Byte 2 of the CPU MAC address. (Default 00)
14.7.4
CPU Address:h303
Accessed by CPU
Bit [7:0] Byte 3 of the CPU MAC address. (Default 00)
14.7.5
CPU Address:h304
Accessed by CPU
Bit [7:0] Byte 4 of the CPU MAC address. (Default 00)
14.7.6
CPU Address:h305
Accessed by CPU
Bit [7:0] Byte 5 of the CPU MAC address. (Default 00).
14.7.7
CPU Address:h306
Accessed by CPU, serial interface (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. ( Default 0xFF)
Bit [7:0]
Bit [0]:
Bit [1]:
Bit [2]:
Bit [7:3]:
MAC2 – CPU Mac address byte 2
MAC3 – CPU Mac address byte 3
MAC4 – CPU Mac address byte 4
MAC5 – CPU Mac address byte 5
INT_MASK0 – Interrupt Mask 0
- 1: Mask the interrupt
- 0: Unmask the interrupt (Enable interrupt)
MASK
•
•
•
•
CPU frame interrupt. CPU frame buffer has data for CPU to read
Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to
read
Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to
read
Reserved
Zarlink Semiconductor Inc.
ZL50418
79
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