zl50418 Zarlink Semiconductor, zl50418 Datasheet - Page 69
zl50418
Manufacturer Part Number
zl50418
Description
Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50418.pdf
(163 pages)
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14.5.2
Registers PVROUTE0 to PVROUTE7 allows the VLAN Index to be assigned an address of a router group. This
feature is useful during IP Multicast mode when data is being sent to the VLAN group and no member of the group
registers. By assigning a router group, the VLAN group always has a default address to handle the multicast traffic.
CPU Address:h171
Accessed by CPU, serial interface (R/W)
PVROUTE 0
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
•
•
•
•
•
•
•
•
Disable Reset PCS (Default = 0)
Support MAC address 0 (Default = 0)
Disable IEEE multicast control frame (0180C2000000 to 0180C20000FF)
to CPU in managed mode (Default = 0)
Multiple MAC addresses (Default = 0)
Disable registers MAC 5 – 0 (CPU MAC address) in comparison with
Ethernet frame destination MAC address. When disable, unicast frames
are not forward to CPU. (Default = 0)
VLAN Index 8’hC0 has router group and the router group is VLAN Index 8’h40
VLAN Index 8’hC1 has router group and the router group is VLAN Index 8’h41
VLAN Index 8’hC2 has router group and the router group is VLAN Index 8’h42
VLAN Index 8’hC3 has router group and the router group is VLAN Index 8’h43
VLAN Index 8’hC4 has router group and the router group is VLAN Index 8’h44
VLAN Index 8’hC5 has router group and the router group is VLAN Index 8’h45
VLAN Index 8’hC6 has router group and the router group is VLAN Index 8’h46
VLAN Index 8’hC7 has router group and the router group is VLAN Index 8’h47
- 0: Enable reset PCS. PCS FIFO will be reset when received a PCS symbol
- 1: Disable reset PCS
- 0: MAC address 0 is not learned.
- 1: MAC address 0 is learned.
- 0: Packet is forwarded to CPU
- 1: Packet is forwarded as multicast
- 0: Single MAC address is assigned to CPU. Registers MAC0 to MAC5 are
- 1: One block of 32 MAC addresses are assigned to CPU. The block is defined
- 1: Disable
- 0: Enable
error.
used to program the CPU MAC address.
in an increase way from the MAC address programmed in registers MAC0 to
MAC5.
Zarlink Semiconductor Inc.
ZL50418
69
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