zl50418 Zarlink Semiconductor, zl50418 Datasheet - Page 109
zl50418
Manufacturer Part Number
zl50418
Description
Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50418.pdf
(163 pages)
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14.12.3
CPU Address:hF03
Accessed by CPU and serial interface (R/W)
14.12.4
CPU Address: hF04
Accessed by CPU and serial interface (RO)
This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Control
Application Note.
Bit[4:0]:
DPST – Device Port Status Register
DTST – Data read back register
7
MD
Read back index register. This is used for selecting what to read back from DTST.
(Default 00)
6
Info
5
Sig
- 5’b00000 - Port 0 Operating mode and Negotiation status
- 5’b00001 - Port 1 Operating mode and Negotiation status
- 5’b00010 - Port 2 Operating mode and Negotiation status
- 5’b00011 - Port 3 Operating mode and Negotiation status
- 5’b00100 - Port 4 Operating mode and Negotiation status
- 5’b00101 - Port 5 Operating mode and Negotiation status
- 5’b00110 - Port 6 Operating mode and Negotiation status
- 5’b00111 - Port 7 Operating mode and Negotiation status
- 5’b01000 - Port 8 Operating mode and Negotiation status
- 5’b01001 - Port 9 Operating mode and Negotiation status
- 5’b01010 - Port 10 Operating mode and Negotiation status
- 5’b01011 - Port 11 Operating mode and Negotiation status
- 5’b01100 - Port 12 Operating mode and Negotiation status
- 5’b01101 - Port 13 Operating mode and Negotiation status
- 5’b01110 - Port 14 Operating mode and Negotiation status
- 5’b01111 - Port 15 Operating mode and Negotiation status
- 5’b10000 - Reserved
- 5’b10001 - Reserved
- 5’b10010 - Reserved
- 5’b00011 - Reserved
- 5’b10100 - Reserved
- 5’b10101 - Reserved
- 5’b10110 - Reserved
- 5’b10111 - Reserved
- 5’b11000 - Port 24 Operating mode/Neg status (CPU port)
- 5’b11001 - Port 25 Operating mode/Neg status (Gigabit 1)
- 5’b11010 - Port 26 Operating mode/Neg status (Gigabit 2)
Zarlink Semiconductor Inc.
4
Giga
ZL50418
109
3
Inkdn
2
FE
1
Fdpx
0
FcEn
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