zl50050 Zarlink Semiconductor, zl50050 Datasheet - Page 6

• Manufacturer Part Number: zl50050
• Description: 8 K-channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16, Or 32 Mbps , And 32 Inputs And 32 Outputs
• Manufacturer: Zarlink Semiconductor

Figure 1 - ZL50050 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50050 PBGA Connections (196 PBGA, 15 mm x 15 mm) Pin Diagram
Figure 3 - 8,192 x 8,192 Channels (16 Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4 - 4,096 x 4,096 Channels (16 Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5 - 6,144 by 2,048 Channels Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7 - Input and Output (Generated) Frame Pulse Alignment for Different Data Rates . . . . . . . . . . . . . . . . . 25
Figure 8 - Backplane and Local Input Channel Delay Timing Diagram (assuming 8 Mbps operation) . . . . . . . . . 27
Figure 9 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mbps . . . . . . . . . . . . . . . . . 28
Figure 10 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Data Rate of
Figure 11 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16 Mbps . . . . . . . . . . . 30
Figure 12 - Local/Backplane Port External High-Impedance Control Bit Timing (Non-32 Mbps Mode). . . . . . . . . 34
Figure 13 - Local and Backplane Port External High-Impedance Control Timing (32 Mbps Mode). . . . . . . . . . . . 38
Figure 14 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch0 . . . . 40
Figure 15 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch13 . . . 40
Figure 16 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch13 Switched to Output Ch0 . . . 40
Figure 17 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch0 . . . . 41
Figure 18 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch13 . . . 41
Figure 19 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch13 Switched to Output Ch0 . . . 41
Figure 20 - Examples of BER Transmission Channels on a 16 Mbps Output Stream . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21 - Hardware RESET De-assertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22 - Frame Boundary Conditions, ST-BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 23 - Frame Boundary Conditions, GCI-Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 24 - Input and Output Clock Timing Diagram for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 25 - Input and Output Clock Timing Diagram for GCI-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 26 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) . . . . . . . . . . . . . . . . . . . . 85
Figure 27 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps). . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 28 - GCI-Bus Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) . . . . . . . . . . . . . . . . . . . 87
Figure 29 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 30 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 31 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 32 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 33 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
(as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
List of Figures
Zarlink Semiconductor Inc.
ZL50050
6
Data Sheet