zl50050 Zarlink Semiconductor, zl50050 Datasheet - Page 15

• Manufacturer Part Number: zl50050
• Description: 8 K-channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16, Or 32 Mbps , And 32 Inputs And 32 Outputs
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Microprocessor Port Signals
Pin Name
LCSTo0-1
D0 - D15
A0 - A14
R/W
DTA
CS
DS
P5, M6, P4, N5,
M5, N2, M4, M3
N7, P7, P6, N6,
P3, P2, N3, N4,
B1, B4, B5, D5,
A3, A4, C6, B6,
A5, A6, C7, B7,
Coordinates
A7, A8, B8
Package
(196-ball
C12, B12
ZL50050
PBGA)
A10
C8
A9
D9
Local Output Channel High-Impedance Control (5 V Tolerant Three-state
Outputs). These pins control external buffering individually for a set of Local
output streams on a per-channel basis.
When LOW, the external output buffer will be tri-stated.
When HIGH, the external output buffer will be enabled.
In Local Non-32 Mbps Mode (stream rate 2 Mbps to 16 Mbps):
LCSTo0 is the output enable for LSTo0,2,4,6,8,10,12,14
LCSTo1 is the output enable for LSTo1,3,5,7,9,11,13,15
In Local 32 Mbps Mode (stream rate 32 Mbps):
LCSTo0 is the output enable for LSTo0,2,4,8
LCSTo1 is the output enable for LSTo1,3,5,7
Refer to descriptions of the LORS and ODE pins for control of the output LOW
or active state.
Address 0 - 14 (5 V Tolerant Inputs). These pins form the 15-bit address bus
to the internal memories and registers.
A0 = LSB
Data Bus 0 - 15 (5 V Tolerant Inputs/Outputs with Slew-Rate Control).
These pins form the 16-bit data bus of the microprocessor port.
D0 = LSB
Chip Select (5 V Tolerant Input). Active LOW input used by the
microprocessor to enable the microprocessor port access. Note that a
minimum of 30 ns must separate the de-assertion of DTA (to high) and
the assertion of CS and/or DS to initiate the next access.
Data Strobe (5 V Tolerant Input). This active LOW input works in conjunction
with CS to enable the microprocessor port read and write operations. Note
that a minimum of 30 ns must separate the de-assertion of DTA (to high)
and the assertion of CS and/or DS to initiate the next access.
Read/Write (5 V Tolerant Input). This input controls the direction of the data
bus lines (D0-D15) during a microprocessor access.
Data Transfer Acknowledgment (5 V Tolerant Three-state Output). This
active LOW output indicates that a data bus transfer is complete. A pull-up
resistor is required to hold a HIGH level. Note that a minimum of 30 ns must
separate the de-assertion of DTA (to high) and the assertion of CS and/or
DS to initiate the next access.
Zarlink Semiconductor Inc.
ZL50050
15
Description
Data Sheet