zl50017 Zarlink Semiconductor, zl50017 Datasheet - Page 15

• Manufacturer Part Number: zl50017
• Description: 1 K Digital Switch
• Manufacturer: Zarlink Semiconductor

The output streams can be programmed to operate as bi-directional streams. By setting BDL (bit 6) in the Internal
Mode Selection (IMS) register, the input streams 0 - 15 (STi0 - 15) are internally tied low, and the output streams 0
- 15 (STio0 - 15) are set to operate in a bi-directional mode.The input data rate is set on a per-stream basis by
programming STIN[n]DR3 - 0 (bits 3 - 0) in the Stream Input Control Register 0 - 15 (SICR0 - 15). The output data
rate is set on a per-stream basis by programming STO[n]DR3 - 0 (bits 3 - 0) in the Stream Output Control Register
0 - 15 (SOCR0 - 15). The output data rates do not have to match or follow the input data rates. The maximum
number of channels switched is limited to 1024 channels. If all 16 input streams were operating at 8.192 Mbps (128
channels per stream), this would result in 2048 channels. Memory limitations prevent the device from operating at
this capacity. A maximum capacity of 1024 channels will occur if four streams are operating at 16.384 Mbps, eight
streams are operating at 8.192 Mbps or all sixteen streams are operating at 4.096 Mbps. With all streams operating
at 2.048 Mbps, the capacity will be reduced to 512 channels. It should be noted that only full streams can be
enabled, the device does not allow partial streams configuration (i.e., cannot have all the streams operating at
16.384 Mbps but only access the half the channels).
4.1
The frequency of the input clock (CKi) for the ZL50017 must be at least twice the input/output data rate. For
example, if the input/output data rate is 8.192 Mbps, the input clock, CKi, must be 16.384 MHz. Following the
example above, if the input/output data rate is 4.096 Mbps, the input clock, CKi, must be 8.192 MHz.The only
exception to this is for 16.384 Mbps input/output data. In this case, the input clock, CKi, is equal to the data rate.
The input frame pulse, FPi, must always follow CKi. CKIN1 - 0 (bits 6 - 5) in the Control Register (CR) are used to
program the width of the input frame pulse and the frequency of the input clock supplied to the device.
The ZL50017 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the
programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the
negative input clock format and ST-BUS format frame pulses. However, the switch can also accept a positive-going
clock format by programming CKINP (bit 8) in the Control Register (CR). A GCI-Bus format frame pulse can be
used by programming FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR).
Input Clock (CKi) and Input Frame Pulse (FPi) Timing
FPi (244 ns)
FPINP = 0
FPINPOS = 0
FPi (244 ns)
FPINP = 1
FPINPOS = 0
FPi (244 ns)
FPINP = 0
FPINPOS = 1
FPi (244 ns)
FPINP = 1
FPINPOS = 1
CKi
(4.096 MHz)
CKINP = 0
CKi
(4.096 MHz)
CKINP = 1
STi
(2.048 Mbps)
Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR
0
Channel 0
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Zarlink Semiconductor Inc.
ZL50017
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15
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Channel 31
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Data Sheet