zl50017 Zarlink Semiconductor, zl50017 Datasheet - Page 14

• Manufacturer Part Number: zl50017
• Description: 1 K Digital Switch
• Manufacturer: Zarlink Semiconductor

3.0
The device has sixteen ST-BUS/GCI-Bus inputs (STi0 - 15) and sixteen ST-BUS/GCI-Bus outputs (STio0 - 15).
STio0 - 15 can also be configured as bi-directional pins, in which case STi0 - 15 will be ignored. It is a non-blocking
digital switch with 1024 64 kbps channels. The ST-BUS/GCI-Bus inputs and outputs accept serial input data
streams with data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps.
By using Zarlink’s message mode capability, microprocessor data stored in the connection memory can be
broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status
information for external circuits or other ST-BUS/GCI-Bus devices.
The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define
the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The
output data streams will be driven by and have their timing defined by FPi and CKi. A Motorola or Intel compatible
non-multiplexed microprocessor port allows users to program the device to operate in various modes under
different switching configurations. Users can use the microprocessor port to perform internal register and memory
read and write operations. The microprocessor port has a 16-bit data bus, a 14-bit address bus and six control
signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY).
The device supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
4.0
The ZL50017 has 16 serial data inputs and 16 serial data outputs. All streams are programmed to operate at
2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32 channels, 64
channels, 128 channels or 256 channels, respectively, during a 125 µs frame.
PBGA Pin
H13, H15,
K13, K15,
J14, H12,
G12, G13
K14, J11,
J15, H11,
J12, J13,
Number
M13
G2
Device Overview
Data Rates and Timing
LQFP Pin
Number
82, 84,
86, 87,
88, 89,
90, 91,
92, 93,
94, 96,
98, 99
211
41
MOT_INTEL
Pin Name
A0 - 13
RESET
Zarlink Semiconductor Inc.
Address 0 to 13 (5 V-Tolerant Inputs)
These pins form the 14-bit address bus to the internal memories
and registers.
Motorola_Intel (5 V-Tolerant Input with Internal Pull-up)
This pin selects the Motorola or Intel microprocessor interface to
be connected to the device. When this pin is unconnected or
connected to high, Motorola interface is assumed. When this pin
is connected to ground, Intel interface should be used.
Device Reset (5 V-Tolerant Input with Internal Pull-up)
This input (active LOW) puts the device in its reset state that
disables the STio0 - 15 drivers. It also preloads registers with
default values and clears all internal counters. To ensure proper
reset action, the reset pin must be low for longer than 1 µs. Upon
releasing the reset signal to the device, the first microprocessor
access cannot take place for at least 500 µs due to the time
required to stabilize the device from the power-down state. Refer
to Section Section 10.2 on page 25 for details.
ZL50017
14
Description
Data Sheet