zl50010 Zarlink Semiconductor, zl50010 Datasheet - Page 41

• Manufacturer Part Number: zl50010
• Description: Flexible 512 Channel Dx With Enhanced Dpll
• Manufacturer: Zarlink Semiconductor

2.11
The following are some synchronizer performance indicators and their definitions. The performance of the DPLL is
also indicated.
2.11.1
Intrinsic jitter is the jitter produced by a synchronizer and is measured at its output. It is measured by applying a
jitter free reference signal to the input of the device, and measuring its output jitter. Intrinsic jitter may also be
measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the
output jitter of the device. Intrinsic jitter is usually measured with various band-limiting filters depending on the
applicable standards.
Intrinsic jitter is applicable only in Master and Freerun modes since in Bypass mode the DPLL is completely
bypassed.
The DPLL’s intrinsic jitter is 6.25 ns peak to peak. The intrinsic jitter will be added to the ST-BUS outputs CKo0-2,
FPo0-2, STo0-15 and STOHZ0-15. Since the DPLL master clock (MCKDPLL) comes from the on chip APLL which
is driven by the oscillator, any jitter on the oscillator will be added unattenuated onto the intrinsic jitter.
2.11.2
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e., remain in lock and/or
regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and the jitter frequency depends on the applicable standards.
The DPLL’s jitter tolerance meets Telcordia GR-1244-CORE DS1 reference input jitter tolerance requirements.
2.11.3
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for
large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter
signals (e.g., 75% of the specified maximum jitter tolerance).
The DPLL’s jitter transfer characteristic is determined by the internal 1.52 Hz low pass Loop Filter and the Phase
Slope Limiter. The DPLL is a second order, Type 2 PLL. Figure 29 on page 42 shows the DPLL jitter transfer
characteristic over a wide range of frequencies, while Figure 30 on page 42 expands the portion of Figure 29
around the 0 dB jitter transfer region. The jitter transfer function can be described as a low pass filter to 1.52 Hz, -
20 dB/decade, with peaking less then 0.5 dB.
2.11.4
Frequency accuracy is defined as the absolute tolerance of an output clock when the synchronizer is not locked to
an external reference, but is in a free running mode.
In Freerun mode, the DPLL is not synchronized to any reference. The DPLL provides output clocks and frame
pulses based on the DPLL master clock. The PLL block’s DCO circuit ignores its frequency offset input and free
runs at its center frequency. Because of the granularity of the center frequency control value, the DCO free run
frequency is -0.03 ppm off the ideal frequency. The DCO is clocked by the DPLL master clock MCKDPLL. The
APLL generates the DPLL master clock from the oscillator. Thus the DPLL free run accuracy is affected by the
oscillator accuracy. The DPLL free run accuracy is -0.03 ppm plus the accuracy of the oscillator.
DPLL Performance
Jitter Transfer
Frequency Accuracy
Intrinsic Jitter
DPLL Jitter Tolerance
Zarlink Semiconductor Inc.
ZL50010
41
Data Sheet