zl50010 Zarlink Semiconductor, zl50010 Datasheet - Page 17

• Manufacturer Part Number: zl50010
• Description: Flexible 512 Channel Dx With Enhanced Dpll
• Manufacturer: Zarlink Semiconductor

Users have to program the CKIN2 - 0 bits in the Control Register (CR), for the width of the frame pulse low cycle
and the frequency of the input clock. See Table 1 for the programming of the CKIN0, CKIN1 and CKIN2 bits in the
Control Register.
The device also accepts positive or negative input frame pulse and ST-BUS input clock formats via the
programming of the FPINP and CKINP bits in the Internal Mode Selection (IMS) register. By default, the device
accepts the negative input clock format.
Figure 4, Figure 5 and Figure 6 describe the usage of CKIN2 - 0, FPINP and CKINP in the Internal Mode Selection
(IMS) register:
(16.384 MHz)
(16.384 MHz)
(4.096 MHz)
(4.096 MHz)
(8.192 MHz)
(8.192 MHz)
CKINP = 1
CKINP = 1
CKINP = 0
CKINP = 0
CKINP = 0
CKINP = 1
FPINP = 0
FPINP = 1
FPINP = 0
FPINP = 1
FPINP = 0
FPINP = 1
CKIN2 - 0 bits
Figure 4 - Input Timing when (CKIN2 to CKIN0 Bits = 010) in the Control Register
Figure 5 - Input Timing when (CKIN2 to CKIN0 Bits = 001) in the Control Register
Figure 6 - Input Timing when (CKIN2 to CKIN0 Bits = 000) in the Control Register
(8 kHz)
011 - 111
CKi
CKi
CKi
CKi
CKi
CKi
FPi
FPi
FPi
FPi
FPi
FPi
000
001
010
FPi Low Cycle
Table 1 - FPi and CKi Input Programming
122 ns
244 ns
Input Frame Boundary
Input Frame Boundary
61 ns
Input Frame Boundary
Zarlink Semiconductor Inc.
Reserved
ZL50010
17
16.384 MHz
8.192 MHz
4.096 MHz
CKi
Highest Input Data Rate
Input Frame Boundary
Input Frame Boundary
Input Frame Boundary
8.192 Mbps
4.096 Mbps
2.048 Mbps
Data Sheet