zl50010 Zarlink Semiconductor, zl50010 Datasheet - Page 37

• Manufacturer Part Number: zl50010
• Description: Flexible 512 Channel Dx With Enhanced Dpll
• Manufacturer: Zarlink Semiconductor

2.10.2
The DPLL accepts two simultaneous reference inputs and operates on their rising edges. The State Machine output
REF_SELECT chooses either the primary reference (PRI_REF_INT signal) or the secondary reference (SEC_REF
signal) as the REF input to the Skew Control circuit. REF_SELECT also selects the frequency mode input
(FREQ_MOD) to the PLL block from either FREQ_MOD_PRI or FREQ_MOD_SEC. These are two bit wide signals
from the DOM register: FREQ_MOD_PRI corresponds to the FP1-0 bits, FREQ_MOD_SEC corresponds to the
FPS1-0 bits.
2.10.3
The Skew Control circuit delays the selected reference input with an 8 tap tapped delay line (see Figure 26). The
nominal delay between taps is 1.9 ns. Thus the selected reference can be delayed by 0 to 13.3 ns in steps of 1.9 ns
(0 to 7 steps). The output tap is selected by SKEW_CONTROL which corresponds to the SKC2-0 bits of the DPLL
Output Adjustment (DPOA) register. Skewing the reference will cause the feedback signal in the PLL block
(FEEDBACK in Figure 28 on page 39) to be delayed by the skew amount with respect to the original reference.
This will cause the DPLL output to be delayed by the skew amount. Hence the ST-BUS outputs will be delayed by
the skew amount.
2.10.4
There are two identical Reference Monitor circuits, one for the primary reference PRI_REF_INT and one for the
secondary reference SEC_REF. Each circuit continuously monitors its reference and reports the reference’s
validity. The output signals are FAIL_PRI and FAIL_SEC for the primary and secondary monitors respectively. A
logic high on either signal indicates that the corresponding reference has become invalid. The validity criteria
depends on the frequency programmed for the reference. A reference must meet all criteria applicable to its
frequency, which are:
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•
•
The FAIL_PRI and FAIL_SEC signals are available at the DHKR register PFD and SFD bits respectively. They are
not affected by the choice of the preferred reference or failure detect mode and will always report the validity of the
primary and secondary references respectively.
The "minimum 90 ns" check is performed regardless of the programmed frequency. Both the logic high and
low duration of the reference must be at least 90 ns.
The "period in specified range" check is performed regardless of the programmed frequency. Each period
must be within a range. For 1.544 MHz and 2.048 MHz, the range is 1-1/4 to 1+1/4 nominal period. For
8 kHz, the range is 1-1/32 to 1+1/32 nominal period.
If the programmed frequency is 1.544 MHz or 2.048 MHz, the "64 periods in specified range" check will be
performed. The time taken for 64 consecutive cycles must be between 62 and 66 periods of the programmed
frequency.
Reference Select and Frequency Mode Mux Circuits
Skew Control Circuit
Reference Monitor Circuit
reference
input
SKEW_CONTROL
Figure 26 - Skew Control Circuit Diagram
Zarlink Semiconductor Inc.
ZL50010
37
delayed
reference
Data Sheet