mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 74

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

7 - 2
7 - 1
Bit
Bit
7 - 0
1
0
0
Bit
Table 84 - HDLC Address Recognition Register 2 (Pages 0BH & 0CH, Address 11H)
(000000)
(000000)
Name
Adr16
Adr11
Adr10
Name
A1en
Ad26
Ad20
A2en
Name
(0)
(0)
(0)
Bit7
Bit0
-
-
-
Table 83 - HDLC Address Recognition Register1
A six bit mask used to interrogate the first byte of the received address.
Adr16 is the MSB.
This bit is used in address comparison, if control bit Seven, bit 4 of HDLC
Control Register 2 (address 15H) is one.
When this bit is high, this six (or seven) bit mask is used in address
comparison of the first address byte.
If address recognition is enabled, any packet failing the address
comparison will not be stored in the RX FIFO. A1en must be high for All-call
(1111111) address recognition for single byte address. When this bit is low,
this bit mask is ignored in address comparison
A seven bit mask used to interrogate the second byte of the received
address. Adr26 is MSB. This mask is ignored (as well as first byte mask) if
all call address (1111111) is received.
When this bit is one, this seven bit mask is used in address comparison of
the second address byte.
If address recognition is enabled, any packet failing the address
comparison will not be stored in the Rx FIFO. A2en must be one for All-call
address recognition. When this bit is zero, this bit mask is ignored in
address comparison
This eight bit word is tagged with the two status bits (EOP and FA) from
the Control Register 1, and the resulting 10 bit word is written to the TX
FIFO. The FIFO status is not changed immediately after a write or read
occurs. It is updated after the data and the read/write pointers have
settled.
Table 85 - TX FIFO Write Register
(Page 0BH & 0CH, Address 10H)
(Pages 0BH & 0CH, Address 12H)
Zarlink Semiconductor Inc.
MT9075B
74
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