mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 32

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

Bipolar Violation Error Counter (BPV15-BPV0)
The bipolar violation error counter will count bipolar violations or encoding errors that are not part of HDB3
encoding. This counter BPV15-BPV0 is 16 bits long (page 04H, addresses 1DH and 1CH) and is incremented once
for every BPV error received. It should be noted that when presetting or clearing the BPV error counter, the least
significant BPV counter address should be written to before the most significant location.
There are two maskable interrupts associated with the bipolar violation error measurement. BPVI (page 01H,
address 1CH) is initiated when the least significant bit of the BPV error counter toggles. BPVO (page 01H, address
1BH) is initiated when the counter changes from FFFFH to 0000H.
CRC Error Counter (CC9-0)
CRC-4 errors are counted by the MT9075B in order to support compliance with ITU-T requirements. This ten bit
counter is located on page 04H, addresses 1EH and 1FH respectively. It is incremented by single error events,
which is a maximum rate of twice per CRC-4 multiframe.
There is a maskable interrupts associated with the CRC error measurement. CRCI (page 01H, address 1CH) is
initiated when the least significant bit of the counter toggles, and CRCO (page 01H, address 1DH) is initiated when
the counter overflows.
Error Insertion
Six types of error conditions can be inserted into the transmit PCM 30 data stream through control bits, which are
located on page 02H, address 10H. These error events include the bipolar violation errors (BPVE), CRC-4 errors
(CRCE), FAS errors (FASE), NFAS errors (NFSE), payload (PERR) and a loss of signal error (LOSE). The LOSE
function overrides the HDB3 encoding function.
Per Time Slot Control
There are two per time slot control pages (page 07H and 08H) occupying a total of 32 unique addresses. Each
address controls a matching timeslot on the 32 transmit channels (onto the line) and the equivalent channel data on
the receive (DSTo) data. For example, address 0 of the first per time slot control page contains program control for
transmit timeslot 0 and DSTo channel 0.
Per Time Slot Looping
Any channel or combination of channels may be looped from transmit (sourced from DSTi) to receive (output on
DSTo) STBUS channels. When bit 4 (LTSL) in the Per Time Slot Control Word is set the data from the equivalent
transmit timeslot is looped back onto the equivalent receive channel.
Any channel or combination of channels may be looped from receive (sourced from the line data) to transmit
(output onto the line) channels. When bit 5 (RTSL) in the Per Time Slot Control Word is set the data from the
equivalent receive timeslot is looped back onto the equivalent transmit channel.
PRBS Testing
If the control bit ADSEQ is zero (from master control page 02H address 13H - Access Control Word), any
channel or combination of transmit channels may be programmed to contain a generated pseudo random bit
sequence (2
1. If the control bit ADSEQ is zero any combination of receive channels may be connected to the PRBS decoder
If the PRBS testing is performed in a metallic or external looparound the Per Time Slot Control Words with TTST
(transmit test, bit 3) set should have RRST (receive test, bit 2) set at the same time.
(2
nels are selected by setting bit 2 (RRST) in the Per Time Slot Control Word.
15
-1). Each error in the incoming sequence causes the PRBS error counter to increment. The receive chan-
15
-1). The channels are selected by setting bit 3 (TTST) in the Per Time Slot Control Word.
Zarlink Semiconductor Inc.
MT9075B
32
Data Sheet