zl30462 Zarlink Semiconductor, zl30462 Datasheet - Page 9

• Manufacturer Part Number: zl30462
• Description: Vibratto-s Dvd Processor Product Brief
• Manufacturer: Zarlink Semiconductor

1.6.1
In this state, the DPLL clocks are stopped and all functions are initialized. The Reset state is entered by pulling the
RESET pin to logic 0 for a minimum of 1 µs. When the RESET pin is pulled back to logic 1, internal logic starts a
625 µs initialization process before switching into the Free-run state (MS2, MS1 = 10). It is recommended that a
module reset is performed immediately after power up, to ensure the ZL30462 is set to a know state.
The RESET function would normally be under the control of the system or host controller, usually in the form of a
microprocessor or FPGA. Alternatively, Figure 5 shows how to connect a simple hardware reset circuit to the
ZL30462.
Reset State
______
RESET == 1
Reset
Notes:
== : equal
!= : not equal
&= : AND operation
0 --> 1 : transition from 0 to 1
unconditional return from
MS2, MS1 == 10 forces
any state to FreeRun
MS2, MS1 != 10
FreeRun
10
Figure 4 - ZL30462 State Machine
{Auto} : Automatic transition
{Manual} : Manual transition
{AHRD} : Automatic Holdover
{MHR} : Manual Holdover
Auto Holdover: Automatic Holdover
Figure 5 - Simple Reset Circuit
ZL30462
MS2, MS1 == 01 or
RSEL change
______
RESET
Zarlink Semiconductor Inc.
Holdover
ZL30462
01
MS2, MS1 == 00
Ref: OK &
{Auto}
8
Rp
1k
10k
R
RSEL change
Vdd
(Locked)
Normal
00
10nF
MS2, MS1
C
State
MS2, MS1 == 00
Ref: OK --> Fail
{Auto}
&
Holdover
Auto
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=1 &
MHR 0 --> 1
{Manual}
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=0 &
{Auto}
Data Sheet