zl30462 Zarlink Semiconductor, zl30462 Datasheet - Page 12

• Manufacturer Part Number: zl30462
• Description: Vibratto-s Dvd Processor Product Brief
• Manufacturer: Zarlink Semiconductor

2.1.2
The Normal to Auto-Holdover to Normal transition will usually happen when the Network Element loses its single
reference clock unexpectedly or when it has two references but switching to the secondary reference is not a
desirable option.
The sequence starts with the unexpected failure of a reference signal shown as transition OK --> FAIL in Figure 7
at a time when ZL30462 operates in Normal mode. This failure is detected at the active input based on the following
FAIL criteria:
•
•
After detecting any of these anomalies on a reference clock the Control State Machine will force the DPLL to
automatically switch into the Auto Holdover state. This condition is flagged by LOCK = 0 and HOLDOVER = 1.
The ZL30462 will automatically return to the Normal state after the reference signal recovers from failure. This
transition is shown on the state diagram as a FAIL --> OK change. This change becomes effective when the
reference is restored and there have been no phase hits detected for at least 64 clock cycles.
This transition from Auto Holdover to Normal state is performed as “hitless” reference switching.
2.1.3
The Normal to Auto-Holdover to Holdover to Normal sequence represents the most likely operation of ZL30462 in
Network Equipment.
The sequence starts from the Normal state and transitions to Auto Holdover state due to an unforeseen loss of
reference. The failure conditions triggering this transition were described in Section 2.1.2. When in the Auto
Holdover state, the ZL30462 can return to Normal state automatically if the lost reference is restored. If the
reference clock failure persists for a period of time that exceeds the system design limit, the system control
processor may initiate a reference switch. If the secondary reference is available the ZL30462 will briefly switch into
Holdover state and then transition to Normal state.
Frequency offset on 8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz reference clocks exceeds ±30000 ppm
(±3%).
Phase hit on 1.544 MHz, 2.048 MHz and 19.44 MHz exceeds half of the cycle of the reference clock.
Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL
Dual Reference Operation: NORMAL --> AUTO HOLDOVER --> HOLDOVER --> NORMAL
Figure 7 - Automatic entry into Auto Holdover State and recovery into Normal mode
______
RESET == 1
Reset
unconditional return from
MS2, MS1 == 10 forces
any state to FreeRun
MS2, MS1 != 10
FreeRun
10
MS2, MS1 == 01 or
RSEL change
Zarlink Semiconductor Inc.
Holdover
ZL30462
01
MS2, MS1 == 00
Ref: OK &
11
{Auto}
Manual return to Normal: AHRD=1 & MHR 0--> 1
Automatic return to Normal: AHDR=0
RSEL change
(Locked)
Normal
00
or
MS2, MS1 == 00
Ref: OK --> Fail
{Auto}
&
Holdover
Auto
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=1 &
MHR 0 --> 1
{Manual}
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=0 &
{Auto}
Data Sheet