zl30462 Zarlink Semiconductor, zl30462 Datasheet - Page 8

• Manufacturer Part Number: zl30462
• Description: Vibratto-s Dvd Processor Product Brief
• Manufacturer: Zarlink Semiconductor

1.5
This circuit monitors both the input reference signals and reports their status automatically to the DPLL. This block
automatically enables the Holdover Mode (Auto-Holdover) when the selected reference is outside the Auto-
Holdover capture range. (See AC Electrical Characteristics - Performance). This includes a complete loss of
incoming signal, or a large frequency shift in the incoming signal. When the incoming signal returns to normal, the
DPLL is returned to Normal Mode with the output signal locked to the input signal. The holdover output signal in the
ZL30462 is based on the incoming signal 30 ms minimum to 60 ms prior to entering the Holdover Mode. The
amount of phase drift while in holdover is negligible because the Holdover Mode is very accurate (e.g., <±0.01 ppm,
relative to the master oscillator frequency). Consequently, the phase delay between the input and output after
switching back to Normal Mode is preserved.
1.6
The ZL30462 Control State Machine supporting the three mandatory clock modes required by any Network
Element that operates in a synchronous network. The simplified version of this state machine is shown in Figure 4
and includes the mandatory states: Free-run, Normal and Holdover. These states are complemented by two
additional states: Reset and Auto Holdover, which are critical to the ZL30462 operation under the changing external
conditions.
These clock modes determine the behavior of a Network Element to the unforeseen changes in the network
synchronization hierarchy. Requirements for clock modes are defined in the international standards e.g.: G.812,
G.813, GR-1244-CORE and GR-253-CORE and they are very strictly enforced by network operators.
Figure 4 also shows how the control input pins - RSEL, MS1, MS2 and RESET interact with the Control State
Machine.
Input Impairment Monitor
Control State Machine
Output Driver
LVPECL
Driver
Note : Vcc = +3.3V
Figure 3 - LVPECL Output Termination Circuit
Zarlink Semiconductor Inc.
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ZL30462
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7
Vcc
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LVPECL
Receiver
Data Sheet