zl30406 Zarlink Semiconductor, zl30406 Datasheet - Page 9

• Manufacturer Part Number: zl30406
• Description: Sonet/sdh Clock Multiplier Pll
• Manufacturer: Zarlink Semiconductor

2.2
2.2.1
The C77oP/N-A, C77oP/N-B, C77oP/N-B, and C77oP/N-D outputs provide differential LVPECL clocks at
77.76 MHz. The LVPECL output drivers require a 50 : termination connected to the VCC-2V source for each
output terminal at the terminating end as shown below. The terminating resistors should be placed as close as
possible to the LVPECL receiver.
2.2.2
The CMLP/N output provides a differential CML/LVDS compatible clock at 19.44 MHz, 38.88 MHz, 77.76 MHz,
155.52 MHz selected with FS1-2 pins. The output drivers require a 50 : load at the terminating end if the receiver
is CML type.
Recommended Interface Circuit
LVPECL to LVPECL Interface
CML to CML Interface
ZL30406
LVPECL
Driver
GND
ZL30406
GND
Driver
CML
VCC
VCC
C77oN-A
C77oP-A
Figure 6 - LVPECL to LVPECL Interface
OC-CLKoN
OC-CLKoP
Figure 7 - CML to CML Interface
Typical resistor values: R1 = 130 :, R2 =82 :
Zarlink Semiconductor Inc.
ZL30406
0.1 uF
0.1 uF
+3.3 V
Z=50 :
Z=50 :
9
+3.3 V
0.1 uF
Z=50 :
Z=50 :
0.1 uF
VCC=+3.3 V
R1
R2
50 :
DC bias source
Low Impedance
R1
R2
50 :
LVPECL
Receiver
CML
Receiver
Data Sheet